# Forum: FPGA, VHDL & Verilog VHDL, Big RGB-generator - needs shortening, algorithms

 Author: Rik (Guest) Posted on: 2013-06-28 23:24
Attached files:

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So. I got this big lump of code. It generates up to 75 numbers (2
digits) on a screen. Now I have 8 rows of "stupid" code (no algorithms),
and I'm sure there must be some easier way.
(Notes:
getalvec is an array (15 downto  0) of 8x8 ram for characters
image is what I project on the screen (to be filtered with some
rgb-values)
index is the current number being drawn. It is used to read from a (75
downto 0) vector if that number should be highlighted or not
)
For the full file, see attachment
  if(2x>=14 AND 2x<30) then if(2y >=140 AND 2y<156) then image := getalvec(0) (63-((x-7) + 8*(x-70) )); index := 1; elsif(2y >=166 AND 2y <182) then image := getalvec(0) (63-((x-7) + 8*(y-83) )); index := 2; elsif(2y >=192 AND 2y<208) then image := getalvec(0) (63-((x-7) + 8*(y-96) )); index := 3; elsif(2y >=218 AND 2y<234) then image := getalvec(0) (63-((x-7) + 8*(y-109) )); index := 4; elsif(2y >=244 AND 2y<260) then image := getalvec(0) (63-((x-7) + 8*(y-122) )); index := 5; elsif(2y >=270 AND 2y<286) then image := getalvec(0) (63-((x-7) + 8*(y-135) )); index := 6; elsif(2y >=296 AND 2y<312) then image := getalvec(0) (63-((x-7) + 8*(y-148) )); index := 7; elsif(2y >=322 AND 2y<338) then image := getalvec(0) (63-((x-7) + 8*(y-161) )); index := 8; else image := '0'; index := 0; end if; elsif(next) %etc.. 

 Author: Rik (Guest) Posted on: 2013-06-28 23:28

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Edit: It's purpose: to put on a FPGA attached to any RGB-monitor and
game around.

 Author: siviano (Guest) Posted on: 2013-06-28 23:46

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why do you send code instead of explaing what you want?
guess If you were able to fully explain whatyou need and write it down
in detail, you will find the solution ourself

get the chaos out of your head and think strait

 Author: FPGA-Professional (Guest) Posted on: 2013-10-25 12:31

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This appears to be a task for an optimized VHDL table

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