EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL, Big RGB-generator - needs shortening, algorithms


von Rik (Guest)


Attached files:

Rate this post
useful
not useful
So. I got this big lump of code. It generates up to 75 numbers (2 
digits) on a screen. Now I have 8 rows of "stupid" code (no algorithms), 
and I'm sure there must be some easier way.
(Notes:
getalvec is an array (15 downto  0) of 8x8 ram for characters
image is what I project on the screen (to be filtered with some 
rgb-values)
index is the current number being drawn. It is used to read from a (75 
downto 0) vector if that number should be highlighted or not
)
For the full file, see attachment
1
  if(2x>=14 AND 2x<30) then
2
    if(2y >=140 AND 2y<156) then
3
      image := getalvec(0) (63-((x-7) + 8*(x-70) ));
4
      index := 1;
5
    elsif(2y >=166 AND 2y <182) then
6
      image := getalvec(0) (63-((x-7) + 8*(y-83) ));
7
      index := 2;
8
    elsif(2y >=192 AND 2y<208) then
9
      image := getalvec(0) (63-((x-7) + 8*(y-96) ));
10
      index := 3;
11
    elsif(2y >=218 AND 2y<234) then
12
      image := getalvec(0) (63-((x-7) + 8*(y-109) ));
13
      index := 4;
14
    elsif(2y >=244 AND 2y<260) then
15
      image := getalvec(0) (63-((x-7) + 8*(y-122) ));
16
      index := 5;
17
    elsif(2y >=270 AND 2y<286) then
18
      image := getalvec(0) (63-((x-7) + 8*(y-135) ));
19
      index := 6;
20
    elsif(2y >=296 AND 2y<312) then
21
      image := getalvec(0) (63-((x-7) + 8*(y-148) ));
22
      index := 7;
23
    elsif(2y >=322 AND 2y<338) then
24
      image := getalvec(0) (63-((x-7) + 8*(y-161) ));
25
      index := 8;
26
    else
27
      image := '0';
28
      index := 0;
29
    end if;
30
  elsif(next) %etc..

von Rik (Guest)


Rate this post
useful
not useful
Edit: It's purpose: to put on a FPGA attached to any RGB-monitor and 
game around.

von siviano (Guest)


Rate this post
useful
not useful
why do you send code instead of explaing what you want?
 guess If you were able to fully explain whatyou need and write it down 
in detail, you will find the solution ourself

get the chaos out of your head and think strait

von FPGA-Professional (Guest)


Rate this post
useful
not useful
This appears to be a task for an optimized VHDL table

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.