Forum: FPGA, VHDL & Verilog scrambler/descrambler vhdl code

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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good morning
Please I would a vhdl code for scrambler/descrambler which takes as 
parameter binary data and the scrambler polynomial generator with its 
intial sequence. Also I would a code for a double polynomial generator 
for example UMTS had two polynomial generator :
P1 (X) = X^17 + X^7 + 1

P2 (X) = X^17 + X^10 + X^7 + X^5 + 1

it joined a scrambler/descrambler matlab code which polynomial generator 
is P (X) = 1 + X^5 + X^12 + X^16
Thx in advance

Author: siwar dammak (Company: ISIMSfax) (siwardammak)
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please help me

Author: Lothar Miller (lkmiller) (Moderator)
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> please help me
Maybe someone will help you, if you start with VHDL coding and ask a 
particular question about a specific problem. But this forum is not 
intended to deliver your homework completely.

Have a look for some LFSR implementations in VHDL. There are plenty of 
them on the web and even each FPGA supplier has a bunch of 
implementations (see Xilinx xapp220, xapp217, xapp211, xapp210, 


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