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Forum: FPGA, VHDL & Verilog propogation delay in two bit full adder failure TBW


Author: Shilpa Vijay (Company: Pillai) (p_shilpavijay)
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I have written code for two bit full adder(structural). i have provided 
2 nsec delay to each gate.1 bit full adder working properly but there is 
failure for two bit full adder .I am attaching the code and test bench 
waveform. please provide me solution as early as possible

Author: Lothar Miller (lkmiller) (Moderator)
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> I am attaching the code
Pls do not attach code as *.docx files!
I will not open such potential virulent files.
Use instead the original *.vhdl file(s).

> but there is failure for two bit full adder
Which one?
From which part/program of the toolchain?

Author: Dinesh Penumetcha (dineshvarma)
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In 2 bit OR gate u had given 20 ns sec delay..
that's nt good practice try to give delay only in test bench

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