EmbDev.net

Forum: FPGA, VHDL & Verilog Multiple assignments in verilog


Author: nelson george (Company: student) (together)
Posted on:

Rate this post
0 useful
not useful
I have written the following verilog codes.....The first one will 
execute in one clock cycle......But due to multiple assignments of 
variable ,the second code is not executing in one clock cycle.....Can 
anyone suggest any method so that the second code also will execute 
fully in one clock cycle????
PLZ HELP


//pgrm 1

always @(posedge clk)
begin

s<=8'h01;
s_rot <= 8'h01;
s_2<= 8'h03;
s_out1<= 8'h01;
s_out2<=8'h01;

end


//pgrm 2

always @(posedge clk)
begin

s<=(DATA_WIDTH-m);
s_rot <= s<<1;
s_2<=s+8'h03;
s_out1<=s_rot+8'h01;
s_out2<=s_rot+s_2;

end

Author: hiall (Guest)
Posted on:

Rate this post
0 useful
not useful
blocking assignments

Author: Ale (Guest)
Posted on:

Rate this post
0 useful
not useful
I'd suggest you get a good learning book about Verilog, and read it at 
least 3 times. The concepts are not difficult but they are different 
from C programming.

You know '<=' is an unblocking assignment, right ? Good:

On the rising edge of the clock all registers will get updated with the 
current values that are on the right.
The values in the first example are fixed, then all registers get those 
values.

On the second example:

First rising edge

1. s_rot gets s shifted 1 to the left
2. s_2 gets s plus 3
3. s_out gets the current value of s (not yet shifted) plus 1
4. s_out2 gets the current value of s plus whatever value s_2 has

Second rising edge

The same as above... now s_out contains the shifted s plus 1...

Author: Ale (Guest)
Posted on:

Rate this post
0 useful
not useful
Get icarus verilog and Gtkwave and simulate everything :)

Author: Ale (Guest)
Posted on:

Rate this post
0 useful
not useful
Ops, I meant for points 3 & 4 s_rot instead of s.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.