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I have written the following verilog codes.....The first one will execute in one clock cycle......But due to multiple assignments of variable ,the second code is not executing in one clock cycle.....Can anyone suggest any method so that the second code also will execute fully in one clock cycle???? PLZ HELP //pgrm 1 always @(posedge clk) begin s<=8'h01; s_rot <= 8'h01; s_2<= 8'h03; s_out1<= 8'h01; s_out2<=8'h01; end //pgrm 2 always @(posedge clk) begin s<=(DATA_WIDTHm); s_rot <= s<<1; s_2<=s+8'h03; s_out1<=s_rot+8'h01; s_out2<=s_rot+s_2; end
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I'd suggest you get a good learning book about Verilog, and read it at least 3 times. The concepts are not difficult but they are different from C programming. You know '<=' is an unblocking assignment, right ? Good: On the rising edge of the clock all registers will get updated with the current values that are on the right. The values in the first example are fixed, then all registers get those values. On the second example: First rising edge 1. s_rot gets s shifted 1 to the left 2. s_2 gets s plus 3 3. s_out gets the current value of s (not yet shifted) plus 1 4. s_out2 gets the current value of s plus whatever value s_2 has Second rising edge The same as above... now s_out contains the shifted s plus 1...
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Get icarus verilog and Gtkwave and simulate everything :)