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Forum: FPGA, VHDL & Verilog error in post place and route simulation


Author: sarmad sarmad (Company: ibtikarat) (sarmad88)
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help me please
my project in VHDL code use the Fixed point package by David Bishop and 
i use the ISE14.1 and spartan3E board and when make post place and route 
simulation the below error occur:


ERROR:HDLCompiler:1316 - 
"G:/project/VHDL/final_with_PAR-simulation/netgen/par/main_timesim.vhd" 
Line 28014: Index value <-16> is out of range [0:2147483647] of array 
<std_logic_vector>
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit 
main in library work failed

and this error occur in the line :

     signal operation_comp_sum30 : STD_LOGIC_VECTOR ( 13 downto -16 );

and i d'not know how can solve this error please any one help me to 
solve this error

Author: Mosfred (Guest)
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change the indices, -16 is giving you the error.
W U N using (29 downto 0) instead of ( 13 downto -16 )?

Regards

: Restored by Admin
Author: sarmad sarmad (Company: ibtikarat) (sarmad88)
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thank you for your answer
but my main_timesim.vhd that created by post place and route simulations 
is content 363873 line of VHDL code
is i must be change all rang for std_logic_vector form (9 downto -16) to 
(29 downto 0) to resolve this erro???????

Author: Duke Scarring (Guest)
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I think there is a special version of this package for synthesis with 
Xilinx/XST.

Duke

Author: sarmad sarmad (Company: ibtikarat) (sarmad88)
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thank you for your answer but i solve the problem by anther way

i write the std_logic_vector1 instead of std-logic_vector

Author: sarmad sarmad (Company: ibtikarat) (sarmad88)
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help me to solve problem in optimization process

hi
why when i use type array signal with initial value in my code the 
utilization summary (number of slices ) become 0%
please how can overcome this problem?????
 Is there a way to stop the optimization process in ISE14.1??????????? 
Because it trimmed many important signals system and this signal no 
appear when make modify conection in chipscope program to debug the 
signal


please any one help me to overcome this problem

Author: Duke Scarring (Guest)
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The synthesizer (xst/ise) will trim all unused signals.
If you use chipscope (why chipscope and not a simulator?), the signal is 
used and not trimed away.

Duke

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