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Forum: FPGA, VHDL & Verilog entity, end of the declaration


Author: Marco (Guest)
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hello,
I don't understand when we must use "end entity" instead of "end 
Name_of_the_entity" in VHDL.

I'm a beginner ;)

Thank you !

Author: Klaus (Guest)
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Never!

Author: user (Guest)
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Read the standard there is defined both "end entity" and "end <name>" 
and also "end entity <name>"

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