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Forum: FPGA, VHDL & Verilog who is familiar with partial reconfiguration of fpgas?


Author: deepak singh (dksagra)
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Hi

Sir, do you have any idea regarding, groups those are working on PARTIAL 
RECONFIGURATION in EUROPE .
As you are pioneer in the field of VHDL and that i know you are from 
EUROPE..so i think you should have some idea.

Thanks and Best Regards

Author: Lothar Miller (lkmiller) (Moderator)
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I'm sorry, but I do not work at or have close contact to universities, 
so I don't have any clue who is working on partial reconfiguration.
This is the very leading edge of technology and as far as I see only a 
better handful of people are working on it.

So try a call around the world:
Who is using partial reconfiguration on FPGAs (or knows one who does)?

Author: SupaChris (Guest)
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I know that a Fraunhofer Institute is working on this. This guys makes 
the Franhofer sattelite "Heinrich Hertz" ready for take off in 2013 and 
as far as I know there is at least one FPGA based subsystem that can be 
partially reconfigured over the "air"...

Author: deepak singh (dksagra)
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Dear Miller,

Thanks for you reply.

Regards

Author: deepak singh (dksagra)
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Dear Supachris,

Thanks for your reply....

it seems a big group and doing work on big project..i dont think they
will guide me..

only small group will guide me i think so

Regards

Author: SupaChris (Guest)
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Yes, maybe. The partial reconfiguration is a very academic topic, I 
think, there are only a few engineers in the world who deal with it.
I´m sorry but I also don´t have contact to such guys.

Author: René Z. (dens)
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As a subnote:
There as rad-hardened Processor with a "On-the-Flight" reconfigurable 
FPGA:

http://www.atmel.com/devices/ATF697FF.aspx

Author: William Ferkes (Guest)
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>As you are pioneer in the field of VHDL
Are you kidding?

Author: deepak singh (dksagra)
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NO m not kidding...its true

Author: nerved (Guest)
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Author: Lothar Miller (lkmiller) (Moderator)
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I changed the title of this thread to a more useful text...

Author: wosnet (Guest)
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You may contact the chair for technical informatics (Lehrstuhl für 
Technische Informatik) at TU Dresden. The group of Prof. Spallek has 
done a lot of research on reconfiguration of FPGAs during runtime.

Author: xgcfx (Guest)
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I have done something with these dynamic partial reconfiguration stuff 
during my diploma thesis 5 years ago. That is a very interesting topic. 
We used Virtex 1/2/4 and ISE 6.1 if I remember correct. That was before 
Xilinx was support partial reconfiguration officially. And it was very 
hard to get the tools to make, what we want. I don't know if it is 
simpler today.

Author: xgcfx (Guest)
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I forgot: That research was done at Fraunhofer EAS in Dresden. And it 
was in conjunction with a project about high level synthesis.

Author: deepak singh (dksagra)
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Dear Nerved

thanks for the weblink.

regards

Author: nerved too (Guest)
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> Dear Nerved
> thanks for the weblink.

***lol***

> The group of Prof. Spallek has
> done a lot of research on reconfiguration of FPGAs during runtime.

Me too, with the result, that P-FPGA-R (partial FPGA reconfig):

a) can save a lot of FPGA space, in dynamical systems, when math algos 
have to change

b) invokes a lot of development time and exponential amount of work for 
testing

c) is totally useless for most applications were big FPGAs are used, 
such as MIL / MED, because of validation issues.

An FPGA which dynamically changes it's behaviour during runtime has to 
be considered like software, and the larger the SW-Part in an FPGA, the 
more formal validation is required.

P-FPGA-R will always stay academic and experimental.

Author: deepak singh (dksagra)
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Dear xgcfx

Thanks for your reply..
Sorry but my query is different.
do you know any group who is wrking in partial reconfiguration in 
europe?


Regards

Author: Thomas Reinemann (Company: abaxor engineering) (abaxor)
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Hi,

about ten years ago, there was a research project (SPP1148) in Germany 
by DFG. Against this background some work related to (dynamic) partial 
reconfiguration has been done. For example a PhD thesis has been 
established



http://edoc.bibliothek.uni-halle.de/servlets/MCRFi...

It is in German.


Tom

Author: deepak singh (dksagra)
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Dear Thomas
Thanks for your reply
Regards,

Author: Duke Scarring (Guest)
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Search for 'partial reconfiguration' on this website:
http://www.fpl2012.org/program-all.shtml

With the names of the authors of this talks and posters you can go and 
search for the recent papers.

Duke

Author: KIT (Guest)
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Author: deepak singh (dksagra)
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Thanks DUKE

Thanks KIT

Author: seennoob (Guest)
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Hallo

The University of Oslo (Department of Informatics) offers some 
publication with the Topic "Dynamic partial reconfiguration of FPGA"

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/

They also have developed a tool for Xilinx devices (Virtex 4,5,6 and 
Spartan 6).

http://www.mn.uio.no/ifi/english/research/projects...


For the hobbyist how will play with that kind of technology, i have find 
a paper for "DPR" on a Spartan 6 (ICAP Interface and so on).

http://www.mn.uio.no/ifi/english/research/projects...

regards Patrick

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