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Forum: FPGA, VHDL & Verilog dvision core..


dvision core..
von deepak s. (dksagra)

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hello,

when i am generating division core ..this particular warning is oming..

WARNING:sim:471 - The chosen IP does not support a VHDL behavioral 
model,
   generating a VHDL structural model instead.
Initialising IP model...
WARNING:sim:472 - The chosen IP does not support a Verilog behavioral 
model,
   generating a Verilog structural model instead.

because of this warning, divion core is not producing any remainder and 
fractional..

please help me..

regards,

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Re: dvision core..
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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> because of this warning, divion core is not producing any remainder
> and fractional..
Why do you think so?
A structural model usually will be "enough" for simulation...

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