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Forum: FPGA, VHDL & Verilog Very simple Verilog array error, fresh eyes appreciated.


Author: AlephOne (Guest)
Posted on:

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I'm designing a single-cycle CPU in Verilog, compiling using Chronologic 
VCS v. 2006 on a Sun Linux server. Below is a trimmed up version of the 
code that's giving me trouble, and the exact verbatim code below is 
still giving me the error:

Parsing design file 'test.v'
Error-[SE] Syntax error
"test.v", 5: token is '['
reg_array[0] = 134;
^
1 error
CPU time: 0 seconds to compile
module regfile;
  
  reg [31:0]  reg_array[0:31]; //array of 32-bit registers

  reg_array[0] = 134;
  reg_array[2] = 854;
  reg_array[6] = 223;
  reg_array[7] = 4878;
  reg_array[8] = 9855;
  reg_array[10] = 2;
  reg_array[20] = 0;
  reg_array[21] = 1;
  reg_array[31] = 5555;

endmodule

I assume it is a painfully simple solution but I am too tired and stupid 
to find it right now. Fresh eyes appreciated. Thanks all!

Author: Lothar Miller (lkmiller) (Moderator)
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> I assume it is a painfully simple solution
I usually do VHDL, but what about the keywords initial or always?
At least this compiles fine:
module regfile;
  
  reg [31:0]  reg_array[0:31]; //array of 32-bit registers

  initial begin
    reg_array[0] = 134;
    :
    :
    reg_array[31] = 5555;
  end 

endmodule

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