1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 | ENTITY buzzer IS
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7 | PORT (
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8 | clk : IN std_logic;
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9 | rst : IN std_logic;
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10 | out_bit : OUT std_logic);
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11 | END buzzer;
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12 |
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13 | ARCHITECTURE arch OF buzzer IS
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14 |
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15 |
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16 | SIGNAL clk_div1 : std_logic_vector(3 DOWNTO 0);
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17 | SIGNAL clk_div2 : std_logic_vector(12 DOWNTO 0);
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18 | SIGNAL cnt : std_logic_vector(21 DOWNTO 0);
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19 | SIGNAL state : std_logic_vector(2 DOWNTO 0);
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20 | CONSTANT duo : std_logic_vector(12 DOWNTO 0) :="0111011101110";
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21 | CONSTANT lai : std_logic_vector(12 DOWNTO 0) := "0110101001101";
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22 | CONSTANT mi : std_logic_vector(12 DOWNTO 0) := "0101111011010";
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23 | CONSTANT fa : std_logic_vector(12 DOWNTO 0) := "0101100110001";
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24 | CONSTANT suo : std_logic_vector(12 DOWNTO 0) := "0100111110111";
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25 | CONSTANT la : std_logic_vector(12 DOWNTO 0) := "0100011100001";
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26 | CONSTANT xi : std_logic_vector(12 DOWNTO 0) := "0011111101000";
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27 | CONSTANT duo1 : std_logic_vector(12 DOWNTO 0) := "0011101110111";
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28 | SIGNAL out_bit_tmp :std_logic;
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29 |
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30 | BEGIN
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31 | out_bit<=out_bit_tmp;
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32 | PROCESS(clk,rst)
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33 | BEGIN
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34 | IF (NOT rst = '1') THEN
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35 | clk_div1 <= "0000";
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36 | ELSif(clk'event and clk='1')then
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37 | IF (clk_div1 /= "1100") THEN
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38 | clk_div1 <= clk_div1 + "0001";
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39 | ELSE
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40 | clk_div1 <= "0000";
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41 | END IF;
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42 | END IF;
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43 | END PROCESS;
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44 |
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45 | PROCESS(clk,rst)
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46 | BEGIN
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47 |
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48 | IF (NOT rst = '1') THEN
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49 | clk_div2 <= "0000000000000";
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50 | state <= "000";
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51 | cnt <= "0000000000000000000000";
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52 | out_bit_tmp <= '0';
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53 | ELSif(clk'event and clk='1')then
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54 | IF (clk_div1 = "1001") THEN
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55 | CASE state IS
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56 | WHEN "000" =>
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57 | cnt <= cnt + "0000000000000000000001";
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58 | IF (cnt = "1111111111111111111111") THEN
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59 | state <= "001";
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60 | END IF;
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61 | IF (clk_div2 /= duo) THEN
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62 | clk_div2 <= clk_div2 + "0000000000001";
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63 | ELSE
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64 | clk_div2 <= "0000000000000";
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65 | out_bit_tmp <= NOT out_bit_tmp;
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66 | END IF;
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67 | WHEN "001" =>
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68 | cnt <= cnt + "0000000000000000000001";
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69 | IF (cnt = "1111111111111111111111") THEN
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70 | state <= "010";
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71 | END IF;
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72 | IF (clk_div2 /=lai) THEN
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73 | clk_div2 <= clk_div2 + "0000000000001";
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74 | ELSE
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75 | clk_div2 <= "0000000000000";
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76 | out_bit_tmp <= NOT out_bit_tmp;
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77 | END IF;
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78 | WHEN "010" =>
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79 | cnt <= cnt + "0000000000000000000001";
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80 | IF (cnt = "1111111111111111111111") THEN
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81 | state <= "011";
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82 | END IF;
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83 | IF (clk_div2 /=mi) THEN
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84 | clk_div2 <= clk_div2 + "0000000000001";
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85 | ELSE
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86 | clk_div2 <= "0000000000000";
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87 | out_bit_tmp <= NOT out_bit_tmp;
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88 | END IF;
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89 | WHEN "011" =>
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90 | cnt <= cnt + "0000000000000000000001";
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91 | IF (cnt = "1111111111111111111111") THEN
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92 | state <= "100";
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93 | END IF;
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94 | IF (clk_div2 /=fa) THEN
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95 | clk_div2 <= clk_div2 + "0000000000001";
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96 | ELSE
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97 | clk_div2 <= "0000000000000";
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98 | out_bit_tmp <= NOT out_bit_tmp;
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99 | END IF;
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100 | WHEN "100" =>
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101 | cnt <= cnt + "0000000000000000000001";
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102 | IF (cnt = "1111111111111111111111") THEN
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103 | state <= "101";
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104 | END IF;
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105 | IF (clk_div2 /=suo) THEN
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106 | clk_div2 <= clk_div2 + "0000000000001";
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107 | ELSE
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108 | clk_div2 <= "0000000000000";
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109 | out_bit_tmp <= NOT out_bit_tmp;
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110 | END IF;
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111 | WHEN "101" =>
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112 | cnt <= cnt + "0000000000000000000001";
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113 | IF (cnt = "1111111111111111111111") THEN
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114 | state <= "110";
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115 | END IF;
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116 | IF (clk_div2 /= la) THEN
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117 | clk_div2 <= clk_div2 + "0000000000001";
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118 | ELSE
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119 | clk_div2 <= "0000000000000";
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120 | out_bit_tmp <= NOT out_bit_tmp;
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121 | END IF;
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122 | WHEN "110" =>
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123 | cnt <= cnt + "0000000000000000000001";
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124 | IF (cnt = "1111111111111111111111") THEN
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125 | state <= "111";
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126 | END IF;
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127 | IF (clk_div2 /= xi) THEN
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128 | clk_div2 <= clk_div2 + "0000000000001";
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129 | ELSE
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130 | clk_div2 <= "0000000000000";
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131 | out_bit_tmp <= NOT out_bit_tmp;
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132 | END IF;
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133 | WHEN "111" =>
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134 | cnt <= cnt + "0000000000000000000001";
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135 | IF (cnt = "1111111111111111111111") THEN
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136 | state <= "000";
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137 | END IF;
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138 | IF (clk_div2 /= duo1) THEN
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139 | clk_div2 <= clk_div2 + "0000000000001";
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140 | ELSE
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141 | clk_div2 <= "0000000000000";
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142 | out_bit_tmp <= NOT out_bit_tmp;
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143 | END IF;
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144 | WHEN OTHERS =>
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145 | NULL;
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146 |
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147 | END CASE;
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148 | END IF;
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149 | END IF;
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150 | END PROCESS;
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151 |
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152 | END arch;
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