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Forum: FPGA, VHDL & Verilog Incrementing/ Decrementing counter does not work


Author: Brian Nguyen (brianpb245)
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I have a program that I am working on that decrements every half second 
and increments every minute , I don't know how to do the clock dividers 
so I am just working on the increase/ decrease of the value and all it 
does it stay at the initial value and doesn't change at all , can 
someone tell me what I am doing wrong

I commented out every counter except one to test it alone, If u need 
more details feel free to ask

Architecture logic of Coolertemp is
  signal cooler: std_logic_vector (6 downto 0);
 
  begin
  process (t_set, c_temp, d,cooler)
   
begin
 
  cooler <= c_temp;
 
  if(d='0')then
    -- cooler <= cooler + "0000001"; --per two minutes (120s)
   
      if(c_temp>t_set) then
        c <= '1';
 
      cooler <= cooler - 1;  --per .5s
    
    end if;
     
   -- if (t_set = cooler + "0000001") then
       -- c <= '0';
 -- end if;

end if;
 
 -- if (d='1') then
   -- c <= '1';
   -- cooler<=cooler+ "0000010" ; --per minute (60s)
   
--end if;

end process;

Author: PittyJ (Guest)
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I'm missing something like a clock.

Author: Lothar Miller (lkmiller) (Moderator)
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cooler <= cooler - 1;  -- per .5s
Do you expect the synthesizer to interpret your comments?
Let me say: thats a stupid code that will never work, but you already 
found the actual problem:
> I don't know how to do the clock dividers
But you ended up in the wrong direction:
> so I am just working on the increase/ decrease of the value

PittyJ already gave a hint: every time (at least all the times > 10ns) 
on a FPGA is based on a counter. So you must implement a counter, that 
counts to  half a second. And with that counter you can increase you 
cooler-value...

> I commented out every counter except one to test it alone
That here:
      cooler <= cooler - 1;  -- per .5s
is not a counter, because there is no clock involved! Its just a very 
unuseful and unwanted thing called "combinational loop" or 
"combinatorial loop" (try these two phrases with google).

Author: Brian Nguyen (brianpb245)
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I have a clock sorry to not include it even with clock it repeats same 
number over and over

Author: Brian Nguyen (brianpb245)
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Architecture logic of Coolertemp is
  signal cooler: std_logic_vector (6 downto 0);
 
  begin
  process (t_set, c_temp, d,cooler,clk)
   
begin
 
  cooler <= c_temp;
 
  if(d='0')then
    -- cooler <= cooler + "0000001"; --per two minutes (120s)
   
      if(c_temp>t_set and clk' event and clk = '1') then
        c <= '1';
 
      cooler <= cooler - 1;  --per .5s
    
    end if;
     

end

Author: Lothar Miller (lkmiller) (Moderator)
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This is a EXTREMELY UNUSUAL description of a clock enable. Have a look 
at all the other VHDL code around the world. Doing it the same way 
will look more like this:
process (clk) begin
  if rising_edge(clk) then
     if(d='0' and cooler >t_set) then
        c <= '1';
        cooler <= cooler - 1;  --per .5s
     end if;
  end if;
end process;

> I have a clock sorry to not include it even with clock it repeats
> same number over and over
And how does that look like? Do you do a simulation (recommended) or do 
you test it on hardware (unusual).

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