module Up_Down(count, up_dwn, clock, reset_); output [2:0] count; input [1:0] up_dwn; input clock, reset_; reg [2:0] count; reg [2:0] state, next_state; parameter state_idle=3'b000, state_inc=3'b010, state_dec=3'b100; always@ (posedge clock or posedge reset_ ) if(reset_) state<=state_idle; else state<=next_state; always @ (state or up_dwn) begin next_state=state; case(state) state_idle: begin //if(up_dwn==2'b00 || up_dwn==2'b11) if(up_dwn==2'b01) begin count<=count+1; next_state=state_inc; end else if(up_dwn==2'b10) begin count<=count-1; next_state=state_dec; end else next_state= state_idle; end state_inc: begin if(up_dwn==2'b01) begin count<=count+1; next_state=state_inc; end else if(up_dwn==2'b10) begin count<=count-1; next_state=state_dec; end else next_state= state_idle; end state_dec: begin if(up_dwn==2'b01) begin count<=count+1; next_state=state_inc; end else if(up_dwn==2'b10) begin count<=count-1; next_state=state_dec; end else next_state= state_idle; end endcase end endmodule
I'm a VHDL guy, but: What about initializing count with 0?
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