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Forum: FPGA, VHDL & Verilog vhdl/verilog code for interfacing DDR3 SDRAM to virtex6 or spartran6 fpga


Author: anjali komalapati (Company: iqi labs) (anjali)
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hi
Can any1 plzzz help me in writing a vhdl/verilog code for interfacing 
DDR3 SDRAM to vertex6 or spartran6 FPGA.
Thank you.

Author: franke (Guest)
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hi

i don't know a device called vertex nor a device spartran6...
(or do you mean virtex and spartan)

but I know, even very experienced designers would not try to build a 
ddr3-controller on their own.
They buy such an IP.

cheers.

Author: anjali komalapati (Company: iqi labs) (anjali)
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ya virtex and spartan by mistake i typed dat....
ok thank you

Author: Christian R. (supachris)
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Why do you want to write this by your own? You can use the Xilinx MIG 
from the ISE Core Generator.

Author: anjali komalapati (Company: iqi labs) (anjali)
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actually in my project there is a use with this DDR3 so i thought of 
writing.
Ok then can u say me any website or any book for understanding DDR3 and 
their interfacing with fpga's......
Thank you.

Author: Raghavendra B. (raghavendra_b98)
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Author: franke (Guest)
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try the micron datasheet...
they are by far the best to understand syncronouse ram's...

Author: anjali komalapati (Company: iqi labs) (anjali)
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HI can any1 say me how to generate a code for DDR3 SDRAM controller from 
MIG core generator of Xilinx.
     I want to write the data to DDR3 SDRAM and i want to Read the data 
from DDR3 SDRAM  for this i have visited opencores i got Synthesizable 
Bfm but is that sufficient for doing this iam unable to get 
clarification. Can any1 please clarify.

    Thank you in advance

Author: anjali komalapati (Company: iqi labs) (anjali)
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Hi can any 1 help me how to write verilog program for interfacing ddr3 
memory to an fpga.
What is the difference between interfacing a ddr3 controller and ddr3 
memory to fpga.
Suppose if we buy a ddr3sdram chip then now if we want to interface that 
to an fpga then How can i proceed for this please.
Thank you.

Author: anjali komalapati (Company: iqi labs) (anjali)
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Hi i have code for this but when iam trying to implementing it shows 
some errors and also. Can any1 please check out this and say me wat to 
do or make some some corrections please

Author: franke (Guest)
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this is really painful

so you found the model of the DDR3-MEMORY in the web and you are not 
able to understand, that this is the SIMULATION-MODEL of a DDR3 memory, 
not of a DD3-memory-controller ?

Author: anjali komalapati (Company: iqi labs) (anjali)
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Ya but for controller can v generate from MIG or what to do iam really 
not understanding what to do. please suggest me....

Author: anjali komalapati (Company: iqi labs) (anjali)
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can you check out this code and suggest me....

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