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Forum: FPGA, VHDL & Verilog vhdl to verilog convert


Author: aa (Guest)
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Hi,

I need to convert this vhdl function in to verilog

FUNCTION EXT (A: STD_LOGIC_VECTOR; SIZE: NATURAL) RETURN 
STD_LOGIC_VECTOR IS
VARIABLE RS: STD_LOGIC_VECTOR (SIZE-1 DOWNTO 0);
VARIABLE TMP: STD_LOGIC_VECTOR (A'length-1 DOWNTO 0);
CONSTANT MSB: natural := min(A'length, SIZE) - 1;
BEGIN
TMP := TO_X01 (A);
RS := (others => '0');
RS(MSB DOWNTO 0) := TMP(MSB DOWNTO 0);
RETURN RS;
END;

Author: Marcus Harnisch (mharnisch)
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In Verilog you don't need to extend a vector explicitly. The language 
does it for you. Defining a function for this wouldn't work anyway, 
since the lengths of parameters and return value must be fixed. Verilog 
doesn't have unconstrained vectors.

Kind regards
Marcus

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