Hi everybody, I'm new to VHDL and I'm doing a project for uni. I'm having problems instatiating a component in a project: I'm trying to build a slow counter by using a clock divider and a 8-bit counter. I'm sure both the counter and the divider work, taken separately. Now, I want to reuse the code for the counter, instatiate the freq div to obtain a "slow counter" driven by the clock. However, the code below yields "output pins stuck to GND or VCC". Can anyone see why ? Thanks library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity slow_cnt2 is port ( clock: in std_logic; rst: in std_logic; Q: out std_logic_vector ( modulus-1 downto 0) ); end slow_cnt2; architecture bhv of slow_cnt2 is signal tcount: std_logic_vector (modulus-1 downto 0); -- inner counter signal slowclk : std_logic; component clk_div is port ( clk: in std_logic; clkout : out std_logic); end component; begin -- bhv divider : clk_div port map ( clk => clock, clkout => slowclk); count: process (slowclk, rst) begin -- process count if rst = '0' then -- asynchronous reset (active low) tcount <= (others => '0'); elsif slowclk'event and slowclk = '1' then tcount <= tcount + '1'; end if; end process count; Q <= tcount; end bhv;
> use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
instead of your lib. numeric_std gives clean interfaces with clean
types.
Can you show us your component clk_div? The other stuff look's not bad
at all.
Duke
Should it be clock => clk, instead of clk => clock, in the port map? Because clk is your input. Port map can also be written as: divider : clk_div port map (clock,slowclk); Because clock goes to clk, the first element in the component description and slowclk to clkout, the second element.
Hi guys, and thanks for your replies. It turned out that the problem was actually a really stupid one, I was compiling the wrong version of the files, due to my inexperience with Quartus, while I was blaming my code, which I didn't trust, again due to inexperience. It took me the best part of a day to realise that ! :O Thanks again for your time.
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