Sensitivity list in VHDL

> 1) Do all input signals for a process have to be listed in the
> sensitivity list?
In common: every signal that requires the simulation to calculate new 
values needs to be in the sensitivity list.

> 2) Are there differences between two logic circuits synthesized
> considering, in the first case, all input signals for a process in
> sensitivity list and part of them in second case?
No, in the best case you will get a warning or a info about a incomplete 
senitvity list. The sensitivity is ONLY for simulation purpose. with a 
incomplete or wrong sensitivity list your simulation can look ok, but 
the generated hardware is completely different.

Take this:

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   signal a,b,clk;

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   process (clk) begin

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      a <= b;

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   end process;

Here your simulation will look as if a is in a kind synchronous to the 
clock. In hardware theres only a wire between a and b...  :-o

Thanks Lothar!

tnx

For not having to care about sensitivity lists in VHDL code, I like the 
language sensitive feature

VHDL > Update > Sensitivity List (Buffer)

supplied by emacs...

>For not having to care about sensitivity lists in VHDL code, I like
> the language sensitive feature
You can also use the corresponding VHDL 2008 all statement:

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  process (all) begin

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     :

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  end process;