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Forum: FPGA, VHDL & Verilog Sensitivity list in VHDL


Author: Mariano Vincenzi (Company: Private) (marvin1473)
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Good morning,

I need some clarifications about sensitivity list in VHDL.

1) Do all input signals for a process have to be listed in the 
sensitivity list?
2) Are there differences between two logic circuits synthesized 
considering, in the first case, all input signals for a process in 
sensitivity list and part of them in second case?

Thank you

Mariano

Author: user (Guest)
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1) for combinatorial logic yes,
   for clocked process only the clock
2) most synthesis tools ignore the sensivity list, giving a warning

Author: Lothar Miller (lkmiller) (Moderator)
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> 1) Do all input signals for a process have to be listed in the
> sensitivity list?
In common: every signal that requires the simulation to calculate new 
values needs to be in the sensitivity list.

> 2) Are there differences between two logic circuits synthesized
> considering, in the first case, all input signals for a process in
> sensitivity list and part of them in second case?
No, in the best case you will get a warning or a info about a incomplete 
senitvity list. The sensitivity is ONLY for simulation purpose. with a 
incomplete or wrong sensitivity list your simulation can look ok, but 
the generated hardware is completely different.

Take this:
   signal a,b,clk;

   process (clk) begin
      a <= b;
   end process;
Here your simulation will look as if a is in a kind synchronous to the 
clock. In hardware theres only a wire between a and b...  :-o

Author: Mariano Vincenzi (Company: Private) (marvin1473)
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Thanks Lothar!

Author: Mariano Vincenzi (Company: Private) (marvin1473)
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tnx

Author: P. K. (pek)
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For not having to care about sensitivity lists in VHDL code, I like the 
language sensitive feature

VHDL > Update > Sensitivity List (Buffer)

supplied by emacs...

Author: Lothar Miller (lkmiller) (Moderator)
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>For not having to care about sensitivity lists in VHDL code, I like
> the language sensitive feature
You can also use the corresponding VHDL 2008 all statement:
  process (all) begin
     :
  end process;

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