EmbDev.net

Forum: FPGA, VHDL & Verilog To many warning


Author: Maurizio Crescini (Company: syntronik) (syntronik)
Posted on:

Rate this post
0 useful
not useful
Hello
I am new of that forum, and also new user and VHDL programmer, but all 
my
programs working but not optimized
I have one counter 7 digit, I use that for read-out linear, whith zero 
point, when I push button, and the zero point arrive, I whant to frozen
the display whith the number in zero point position, but inside the 
chip, the counters have to work normaly, when I push for second time the 
button,
the number chenge whith real condition of counter.
I using EPM240 Altera, and now working perfect, but I have one kilometer
of warning, the help said


CAUSE: The Quartus  II software has found latches implemented using 
non-optimal resources (LUTs with combinational feedback). Timing 
Analysis will replace the combinational loop with an equivalent latch. 
Timing Analysis will now see this logic as a synchronous endpoint, and 
will not analyze the path through the node.

ACTION: Altera recommends that you do not implement latches using 
combinational logic. Implement them instead with registers using 
asynchronous load and data signals, or remove them from your design.

How I can do, or hiw I have to modify my software??
Thanks in advance
Maurizio

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> modify my software??
First: VHDL code is NO software. Its a hardware description language.

> How I can do, or hiw I have to modify my software??
Just attach your code. Otherwise it makes no sense to give any hints...

Try this page with babelfish or google translator (from German):
http://www.lothar-miller.de/s9y/categories/36-Komb...

Author: Maurizio Crescini (Company: syntronik) (syntronik)
Posted on:

Rate this post
0 useful
not useful
First: VHDL code is NO software. Its a hardware description language.

Yes for you is not sofware, I know that, is hardware descrption, but 
it's like a software, where you write instructions like all others 
software, and that instructions convert yours descriptions in hardware, 
for that,
if you have no licence, and you use the quartusII web edition, the 
Altera suggest
"By licence software", can please to suggest to Altera, change in
"By licence for hardware description language".
About the file attachment, I think do not need, to see the list, just 
whith your answer, means, you are not able to give any hints
Thanks
regards
Maurizio

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> "By licence software", can please to suggest to Altera, change in
> "By licence for hardware description language".
No, there you can buy the software for translating your hardware 
description (maybe in Verilog or VHDL) to a bit stream. This software 
you can buy from Altera is also known as "toolchain". You can/do not buy 
a license for any hardware description language, because VHDL is a IEEE 
standard.

> About the file attachment, I think do not need, to see the list, just
> whith your answer,
You're very self confident...  :-/
Good luck for your further life.

> means, you are not able to give any hints
Nice to hear your personal opinion. But for one you can be sure: I would 
be able to. I already made most of your mistakes and doubtless much 
more. And after that I figured out why.

> Thanks
You are welcome.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.