if you have an if statement with a condition: use ieee.std_logic_1164.all; ... signal x, y : std_logic; ... if(x = '1' AND y = '1') then The "=" operator will return a boolean value, which simplifies the matter to any case with: if([boolean] AND [boolean]) then Since VHDL is a strong-typed language, I assumed that the ieee.std_logic_1164 library would contain a definition for the "and" function with boolean arguments, but I cannot find it. The only arguments are for std_logic_vector, signed, and unsigned types. I don't think that VHDL would automatically cast TRUE as '1' and FALSE as '0' either, as that is not always the case. Does anyone have some insight as to how this issue is resolved in VHDL during compilation? Thanks
I don't have a certain answer for you... just a guess. Many VHDL operators are overloaded in different libraries. Perhaps the "AND" operator is overloaded to handle boolean values as well...
Yup, see: http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html#_Toc526061361 Logical operators are defined for boolean AND (pun intended) std_logic (among others)
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