EmbDev.net

Forum: FPGA, VHDL & Verilog Problems with my Code


Author: Adrian McInti (bananacode)
Posted on:

Rate this post
0 useful
not useful
Hey guys

I've been having problems with my code.

I'm trying to create a FSM with the following modules, each in a 
separate source file:

module ClockCounter(
    input clk,
    input rst,
    output clk_en
    );
reg [24:0] clk_count;

always @ (posedge clk, posedge rst)
begin
if (rst) clk_count <= 0;
  else clk_count <= clk_count+'b1;
end
assign clk_en = &clk_count;

endmodule


module OutputLogic(
    input [2:0] S,
    output reg LA, LB, LC, RA, RB, RC

    );

always @ ( * )
begin
LA <= ~S[0] & S[1] & S[2] | S[0] & S[1] & ~S[2] | S[0] & ~S[1] & S[2];
LB <= S[0] & S[1] & ~S[2] | S[0] & ~S[1] & S[2];
LC <= S[0] & ~S[1] & S[2];

RA <= ~S[0] & ~S[1] & S[2] | ~S[0] & S[1] & ~S[2] | S[0] & ~S[1] & 
~S[2];
RB <= ~S[0] & S[1] & ~S[2] | S[0] & ~S[1] & ~S[2];
RC <= S[0] & S[1] & ~S[2];
end

endmodule

module StateHoldingRegister(
    input [2:0] SN,
    input CLK,
    output reg [2:0] S
    );

always @ (posedge CLK)

S <= SN;



endmodule

module NextStateLogic(
    input [2:0] S,
    input L,
    input R,
    output reg [2:0] SN
    );

always @ ( * )

begin
SN [0] <= ~S[0] & S[1] | S[1] & ~S[2];
SN [1] <= S[0] & S[1] & S[2] & L & ~R | ~S[0] & S[2];
SN [2] <= ~S[0] & ~S[1] & ~S[2] & ~L & R | ~S[0] & ~S[1] & ~S[2] & L & 
~R | S[0] & S[1] & ~S[2];
end
endmodule


I have no idea how to connect them via verilog, so I created a schematic 
symbol for each and connected them via a new schematic source file.

However, I get this error:

ERROR:HDLCompilers:91 - "Thunderbird.vf" line 53 Module 
'NextStateLogic_MUSER_Thunderbird' does not have a port named 'L'
ERROR:HDLCompilers:91 - "Thunderbird.vf" line 54 Module 
'NextStateLogic_MUSER_Thunderbird' does not have a port named 'R'
ERROR:HDLCompilers:91 - "Thunderbird.vf" line 55 Module 
'NextStateLogic_MUSER_Thunderbird' does not have a port named 'S'
ERROR:HDLCompilers:91 - "Thunderbird.vf" line 56 Module 
'NextStateLogic_MUSER_Thunderbird' does not have a port named 'SN'

My question to you guys is, what's my mistake? How can I connect the 
modules through verilog?

Regards

Author: Na sowas (Guest)
Posted on:

Rate this post
0 useful
not useful
Id do not know about Verilog, but I found the actual problem:
> I have no idea how to connect them via verilog
Look how others are doing it. I expect the solution for your problem in 
the very first quarter of any Verilog book!

Author: Adrian McInti (bananacode)
Posted on:

Rate this post
0 useful
not useful
As stupid as it may sound, I've searched the net looking for code and 
examples on how to connect, even looked at a digital circuit book, I did 
not find it. I'd be very grateful if you could link me to a site which 
says how to..

Author: bko (Guest)
Posted on:

Rate this post
0 useful
not useful
http://www.verilog.renerta.com/source/vrg00027.htm

for example (but I have not done a syntax check)
[verilog]
module connect_them(
    input clk_from_xtal),
    input L_in,
    input R_in,
    output clk_en
    );

wire [2:0] SN_from_other_module;
wire [2:0] S_to_elsewhere);
wire [2:0] SN_to_othermodule;

 StateHoldingRegister  instance_name_1(
    .SN(SN_from_other_module,
   .clk(clk_from_xtal),
   .S(S_to_elsewhere)
    );

NextStateLogic instance_name_2(
    .S(S_to_elsewhere)),
    .L(L_in),
    .R(R_in),
    .SN(SN_to_othermodule)
    );

///.... an so on
[/verilog]

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.