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Author: Aiko Yuri (aiko89)
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pin planner for the output that i left blank... can help mie?? Thank you 
in advance...

Author: Aiko Yuri (aiko89)
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this is the picture

Author: Aiko Yuri (aiko89)
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Warning: Found 5 output pins without output pin load capacitance 
assignment
  Info: Pin "note[0]" has no specified output pin load capacitance -- 
assuming default load capacitance of 0 pF for timing analysis
  Info: Pin "note[1]" has no specified output pin load capacitance -- 
assuming default load capacitance of 0 pF for timing analysis
  Info: Pin "note[2]" has no specified output pin load capacitance -- 
assuming default load capacitance of 0 pF for timing analysis
  Info: Pin "note[3]" has no specified output pin load capacitance -- 
assuming default load capacitance of 0 pF for timing analysis
  Info: Pin "speak" has no specified output pin load capacitance -- 
assuming default load capacitance of 0 pF for timing analysis

Author: Aiko Yuri (aiko89)
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module music(
    input wire nrst,    //reset signal
    input wire clk,     //source clock 5Mhz

    output reg [3:0]note, //index of musical note currently being played
    output wire speak   //sound enable
);

//enable sound if current note is not zero index
assign speak = (note !=0);

//one musical step clock counters
reg [20:0]counter;
reg one_step;
reg [4:0]music_time;
//define length of musical step

always @(posedge clk)
begin
    if(counter==5000000/4)
        begin counter <= 0; one_step <= 1'b1; end
    else
        begin counter <= counter + 1'b1; one_step <= 1'b0; end
end

//musical time register



always @(posedge clk or negedge nrst)
begin
    if(nrst==1'b0)
    begin
        //reset
        music_time <= 0;
        note <= 0;
    end
    else
    begin
        //play music here, move musical step forward every music time 
step

        if(one_step)
        begin
            case(music_time)
                0: begin note <=3;  music_time <= music_time+1'b1; end
                1: begin note <=6;  music_time <= music_time+1'b1; end
                2: begin note <=10;  music_time <= music_time+1'b1; end
                3: begin note <=6;  music_time <= music_time+1'b1; end

                4: begin note <=8;  music_time <= music_time+1'b1; end
                5: begin note <=8;  music_time <= music_time+1'b1; end
                6: begin note <=6; music_time <= music_time+1'b1; end
                7: begin note <=5; music_time <= music_time+1'b1; end

                8: begin note <=10; music_time <= music_time+1'b1; end
                9: begin note <=10; music_time <= music_time+1'b1; end
                10:begin note <=8; music_time <= music_time+1'b1; end
                11:begin note <=8; music_time <= music_time+1'b1; end

                12:begin note <=3; music_time <= music_time+1'b1; end
                13:begin note <=3; music_time <= music_time+1'b1; end
                14:begin note <=3; music_time <= music_time+1'b1; end
                15:begin note <=3; music_time <= music_time+1'b1; end
            default:
                //end of music

                begin note <= 0; music_time <= music_time; end
            endcase
        end
    end
end

endmodule

Author: Aiko Yuri (aiko89)
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//NOTE FREQUENCY SYNTEZATOR

module note_synt(
    input wire clk,       //source clock 5Mhz
    input wire [3:0]note, //ID of note


                        //output freq grid
                        //basic freq is note A = 440Hz
                       //every next note differs by 2^(-1/12)
                        //C     523,2511306 Hz
                        //C#    554,3652620 Hz
                        //D     587,3295358 Hz
                        //D#    622,2539674 Hz
                        //E     659,2551138 Hz
                        //F     698,4564629 Hz
                        //F#    739,9888454 Hz
                        //G     783,9908720 Hz
                        //G#    830,6093952 Hz
                        //A     880 Hz
                        //A#    932,327523  Hz
                        //H     987,7666025 Hz
                        //C     1046,502261 Hz
    output reg note_clock,      //generated note clock
    output reg [7:0]note_leds   //blink LEDs
);

//divide coeff
reg [13:0]factor;

//select divide coefficient according to current note being played
always @*
begin
    case(note)
        1:  begin factor = 9560; note_leds = 8'b00000001; end   //C
        2:  begin factor = 9025; note_leds = 8'b00000011; end   //C#
        3:  begin factor = 8518; note_leds = 8'b00000010; end   //D
        4:  begin factor = 8039; note_leds = 8'b00000110; end   //D#
        5:  begin factor = 7587; note_leds = 8'b00000100; end   //E
        6:  begin factor = 7163; note_leds = 8'b00001000; end   //F
        7:  begin factor = 6766; note_leds = 8'b00011000; end   //F#
        8:  begin factor = 6378; note_leds = 8'b00010000; end   //G
        9:  begin factor = 6017; note_leds = 8'b00110000; end   //G#
        10: begin factor = 5682; note_leds = 8'b00100000; end   //A
        11: begin factor = 5364; note_leds = 8'b01100000; end   //A#
        12: begin factor = 5066; note_leds = 8'b01000000; end   //B
    default: begin factor = 1;   note_leds = 8'b00000000; end 
//nothing
        endcase
end

reg eocnt;
reg [13:0]cnt;
always @(posedge clk)
    eocnt <= (cnt == factor);

always @(posedge clk or posedge eocnt)
begin
    if(eocnt)
        cnt <= 0;
    else
        cnt <= cnt + 1'b1;
end

//output sound frequency
always @(posedge eocnt)
    note_clock <= note_clock ^ 1'b1;

endmodule

Author: Duke Scarring (Guest)
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Info: Pin "note[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Hey, read slowly. This message is not an error. Take a look in the tool 
docs[1].

Duke


[1] 
http://quartushelp.altera.com/10.1/master.htm#merg...

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