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Forum: FPGA, VHDL & Verilog usage of parameters in size spec ?


Author: Vivek Mishra (Company: Student) (vivekm12004)
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Hi,

This is a query on Verilog usage. If this is not the appropriate forum
for this type of query, please ignore this request.

Can I use parameters as part of the size specification for a sized
number ? My simulator (gplcver), gives error. e.g. :-
***
parameter DATA_WIDTH = 8;

// o/p to external bus
assign data = (CS && !WR) ? data_out : DATA_WIDTH'bz;
***

I wish to avoid `defines in verilog source.

-- Thanks, V

Author: Hans (Guest)
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Hi,

just use
{DATA_WIDTH{1'bz}}
instead of
DATA_WIDTH'bz
This will replicate the 1'bz the number of times specified by the 
parameter.

Author: Vivek Mishra (Company: Student) (vivekm12004)
Posted on:

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Thanks Hans ! I have made a note of the replication operator.
-- V

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