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Forum: FPGA, VHDL & Verilog strange behaviour of PROCESS


Author: Andrew Kovalenko (andrewk)
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Hi,
I don't understand, why does PROCESS work if it's impossible to work. 
Simplified code described below.
There is unused input "unused_test" which is in sensitivty list of 
PROCESS. I activate simulator in Altera Quartus II (v9.1) with clock 
pulses on input "clk" while input "unused_test" is always zero.
And I see in simulator that output "outp" is negation of wafeform on 
input "clk", i.e. "outp" changes its state as described inside PROCESS.
How can static input "unused_test" activate PROCESS ?????


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY ques IS
PORT( unused_test: IN STD_LOGIC;
    clk: IN STD_LOGIC;
    outp: OUT STD_LOGIC);
END ques;

ARCHITECTURE arch OF ques IS
  SIGNAL prom: STD_LOGIC := '0';
BEGIN
  PROCESS(unused_test)
  BEGIN
  prom <= NOT clk ;
  END PROCESS;
outp <= prom;
END arch;

Author: Na sowas (Guest)
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To get things right:
The sensitivity list is wrong.
  PROCESS(unused_test)  -- wrong
  PROCESS(clk)          -- correct
  BEGIN
    prom <= NOT clk ;
  END PROCESS;
> And I see in simulator that output "outp" is negation of wafeform on
> input "clk", i.e. "outp" changes its state as described inside PROCESS.
The autocompletion of a sensitivity list is what a synthesizer does 
automatically. Look for an info or a warning like:
"incomplete sensitivity list corrected"

> I activate simulator in Altera Quartus II (v9.1)
I suppose this behaviour is because Quartus is a synthesis toolchain in 
first line.

Author: Andrew Kovalenko (andrewk)
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Na sowas, thank you for reply.
Really, synthesizer does autocompletion of a sensitivity list.
But it may be necessary to have only selected signals in sensitivity 
list. And there is no settings to turn off "autocompletion" in 
QuartusII.

Author: Na sowas (Guest)
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> But it may be necessary to have only selected signals in sensitivity
> list.
Then the sensitivity list ist wrong and therefor the simulation is 
wrong.

Keep in mind:
This list is not a way to get different behaviour by choosing some 
selected entries. Every signal that changes the results of the process 
MUST be in the list. Otherwise the simulation simply is WRONG (although 
it may look nice to you). Its definitly not up to you to choose some 
signals.

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