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Forum: FPGA, VHDL & Verilog using subtype


using subtype
von Wafa (Guest)

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good morning,

am obliged to define the type t_pnet_data before the architecture to be 
able to use it in ports types, this is a part of the code :



library ieee;
use ieee.std_logic_1164.all;


subtype t_pnet_data is std_logic_vector(7 downto 0);

type net_frame is record
   low : t_pnet_data;
   high : t_pnet_data;
end record net_frame;

entity pnet_write is
    port(
        p_net_data_in     : in std_logic_vector(7 downto 0);
        p_net_data_valid  : in std_logic;
        p_net_data_read   : out std_logic;
        p_cpu_data_out    : out std_logic_vector(7 downto 0);
        p_cpu_data_valid  : out std_logic;
        p_cpu_data_read   : in std_logic;
        p_cpu_parity      : out std_logic;
        p_retx_data_out   : out net_frame;
        p_retx_data_valid : out std_logic;
        p_retx_data_read  : in std_logic
        );
end pnet_write;

architecture write of pnet_write is
    begin
- - - - - -


and this the error :

** Error: C:/Modeltech_6.2d/examples/pnet_write.vhd(5): near "subtype": 
expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE


what can i do ?!

best regards

Wafa

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Re: using subtype
von Mathi (Guest)

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You cannot define a type outside the entity- or architecture.
When you need such a type, you have to define it in a package and "use" 
the package.

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Re: using subtype
von Wafa (Guest)

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can give me an example please ?!

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Re: using subtype
von Mathi (Guest)

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Create new file with

1
library ieee;

2
use ieee.std_logic_1164.all;

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package my_data_types is

5
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subtype t_pnet_data is std_logic_vector(7 downto 0);

7
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type net_frame is record

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   low : t_pnet_data;

10
   high : t_pnet_data;

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end record net_frame;

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end package my_data_types;


In your design you write
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library ieee;

2
use ieee.std_logic_1164.all;

3
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use work.my_data_types.all; -- <-- your package in standard library work

5
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entity pnet_write is

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    port(

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        p_net_data_in     : in std_logic_vector(7 downto 0);

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        p_net_data_valid  : in std_logic;

10
        p_net_data_read   : out std_logic;

11
        p_cpu_data_out    : out std_logic_vector(7 downto 0);

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        p_cpu_data_valid  : out std_logic;

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        p_cpu_data_read   : in std_logic;

14
        p_cpu_parity      : out std_logic;

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        p_retx_data_out   : out net_frame;

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        p_retx_data_valid : out std_logic;

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        p_retx_data_read  : in std_logic

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        );

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end pnet_write;


To get more information, just type "vhdl package" in google ;)

  


  




  

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      von
      
        Wafa (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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i found it thank you :)

  


  




  

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