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Forum: FPGA, VHDL & Verilog calling a process


Author: Wafa (Guest)
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Good morning,

is it possible in an architecture to call a process several times only 
by changing its variables ?!
for example, if i have a process called calculate

calculate:process(A,B,C)
 begin
C<=A+B;
end process calculate;

then i want to use the same process for D,E and F

is it possible to call calculate without writing the instructions again?
if its possible,how ?

best regards


Wafa

Author: Na sowas (Guest)
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What you need is a function for calculate.

> calculate:process(A,B,C)
>  begin
>  C<=A+B;
> end process calculate;
> then i want to use the same process for D,E and F
> is it possible to call calculate without writing the instructions again?
You do not call a process.
The process above is sensitive on A, B and C.

> is it possible in an architecture to call a process several times only
> by changing its variables ?!
These aren't variables but signals!

But for this here:
calculate:process(A,B,C)
   begin
   C<=A+B;
end process calculate;
you do not need a process at all. Write it down this way:
   C<=A+B;
Thats the concurrent style.

Author: Wafa (Guest)
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u didnt realy answer my question,  i know A B and C are signals,
 u said  i need a function , so how can i write this and call it for D E 
and F  ?!

thank you

Author: Na sowas (Guest)
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> u didnt realy answer my question
Because the question itself doen't make much sense...
In the process
calculate: process(A,B,C)
the Symbols A, B, and C are not parameters that are handed over to the 
process. The are just flags, which say to recalculate the process on 
every change of each of them.

>  i need a function , so how can i write this
function calculate (da : std_logic_vector, db : std_logic_vector)
                           return std_logic_vector is
  variable t : std_logic_vector := '0';  
begin
  t := da + db;  -- higly dependent on libraries
  return t;
end calculate ;
:
:  
  c <= calculate(a,b);
  f <= calculate(d,e);
But what about typing in the words function+vhdl into google?


On the other hand duplicating ressources can be done with a generate 
statement or a loop.

Author: Wafa (Guest)
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Thank you realy much :)

Author: Bernd (Guest)
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regarding functions in VHDL:

keep in mind that the output of synthesis tools has to be watched 
carefully if you use high-level vhdl constructs like functions...

the output may in some cases be not very effective or not of that kind 
as you expected

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