Hi Friends,

I am from Turkey. I take VHDL lessons in my university and I have a term 
project for this lesson.

In this project, I have 2 bit input and four n-bit register 4th register 
is a temporary register and when my two bit input is "00" my n-bit 
registers save their values. then it is "01" R2's value is copied into 
Temp register,then R1's value is copied to R2 register and Temp's value 
is copied into R1 register. when it is "10" same things happen between 
R1 and R3 register and lastly when it is "11" same things happen again 
R2 and R3 registers. I wrote all codes of my project but Some things 
goes wrong because if 2bit input changes when wrong time every register 
lose their values and maybe every register have one value I want to 
restart my shift register when 2 bit input changes. then if I change the 
2 bit input it restart the give enable bits to my registers. I will 
paste my vhdl code below. Please give me some solutions.

I tried to evade from this problem with writing this code:w is 2 bit 
input
Regularstarting is used for the restart the registers enable inputs
rglr:process(w,Clock)
begin
if w(0)'Event and w(0)='1' then
Regularstarting<='1';
elsif w(1)'Event and w(1)='1' then
Regularstarting<='1';
else
Regularstarting<='0';
end if;
end process;
When I simulate this with Xilinx 9.2i there is no problem but if I click 
on the Synthesize then it gives error:(

ERROR:Xst:827 - "C:/VHDL/XilinX/Proje/eightforty.vhd" line 160: Signal 
Regularstarting cannot be synthesized, bad synchronous description.
-->
I developed my code. when my registers swaping then it writes on the 
sevensegment it writes svap when swapping is done then is writes done. 
The data in the bus can be seen with dividing the clock(with changing 
number of bits of countforclk) this code is ready for every thing. I 
have only one problem the values of the registers can be lost if I 
change 2 bit input wrong time to evade this problem I have to restart 
enable inputs of registers

This is my main code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.comps.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eightforty is
generic(M:integer: = ;
Port ( Data :in STD_LOGIC_VECTOR(M-1 downto 0);
Extern,Resetn : in STD_LOGIC;
Clock : in STD_LOGIC;
Deneme :out STD_LOGIC_VECTOR(2 downto 0);
svnsgmnt:out STD_LOGIC_VECTOR(0 to 6);
an1,an2,an3,an4:inout STD_LOGIC:='0';
w : in STD_LOGIC_VECTOR (1 downto 0);
Buswires : inout STD_LOGIC_VECTOR (M-1 downto 0));
end eightforty;

architecture Behavioral of eightforty is
signal R1 :STD_LOGIC_VECTOR(M-1 downto 0):="00001001";
signal R2 :STD_LOGIC_VECTOR(M-1 downto 0):="11111111";
signal R3 :STD_LOGIC_VECTOR(M-1 downto 0):="11000000";
signal Temp :STD_LOGIC_VECTOR(M-1 downto 0):="00000000";
signal Q :STD_LOGIC_VECTOR(3 downto 1);
signal countforsvn:STD_LOGIC_VECTOR(1 downto 0):="00";
signal countforclk:STD_LOGIC_VECTOR(3 downto 0):=(OTHERS=>'0');
signal Clock3hz:STD_LOGIC:='0';
signal Done :STD_LOGIC:='0';
signal Rin,Rout :STD_LOGIC_VECTOR(3 downto 1):="000";
signal Tempin,Tempout :STD_LOGIC;
signal Regularstarting:STD_LOGIC:='0';
begin

cnt4clk:process(Clock)
begin
if Clock'Event and Clock='1' then
if Resetn='1' then
countforclk<=(OTHERS=>'0');
else
countforclk<=countforclk+1;
end if;
end if;
end process cnt4clk;

Clock3hz<=countforclk(3);

cntr:process(clock)
begin
if Clock'Event and Clock='1' then

countforsvn<=countforsvn+'1';

if countforsvn="00" then
an1<='1';
an2<='0';
an3<='0';
an4<='0';
elsif countforsvn="01" then
an1<='0';
an2<='1';
an3<='0';
an4<='0';
elsif countforsvn="10" then
an1<='0';
an2<='0';
an3<='1';
an4<='0';
elsif countforsvn="11" then
an1<='0';
an2<='0';
an3<='0';
an4<='1';
countforsvn<="00";
end if;

end if;
end process cntr;
writetosvn:process(Clock)
begin
if Done='0' then

if an1='1' then
svnsgmnt<="0100100";
elsif an2='1' then
svnsgmnt<="1100011";
elsif an3='1' then
svnsgmnt<="0001000";
elsif an4='1' then
svnsgmnt<="0011000";
else
svnsgmnt<="0000000";
end if;

elsif Done='1' then

if an1='1' then
svnsgmnt<="1000010";
elsif an2='1' then
svnsgmnt<="1100010";
elsif an3='1' then
svnsgmnt<="1101010";
elsif an4='1' then
svnsgmnt<="0110000";
end if;

end if;
end process writetosvn;


CntrlCrct:CntrlCrt generic map(K=>3)
port map(Regularstarting,Clock3hz,Q);

rglr:process(w,Clock)
begin
if w(0)'Event and w(0)='1' then
Regularstarting<='1';
elsif w(1)'Event and w(1)='1' then
Regularstarting<='1';

else
Regularstarting<='0';
end if;
end process;
selection:process(w,Q)
begin
if w(1)='0' and w(0)='1' and Resetn='0' then


Tempin<=Q(1);
Rout(2)<=Q(1);
Rin(2)<=Q(2);
Rout(1)<=Q(2);
Rin(1)<=Q(3);
Tempout<=Q(3);
Rout(3)<='0';
Rin(3)<='0';




elsif w(1)='1' and w(0)='0' and Resetn='0' then


Tempin<=Q(1);
Rout(3)<=Q(1);
Rin(3)<=Q(2);
Rout(1)<=Q(2);
Rin(1)<=Q(3);
Tempout<=Q(3);
Rout(2)<='0';
Rin(2)<='0';


elsif w(1)='1' and w(0)='1' and Resetn='0' then


Tempin<=Q(1);
Rout(3)<=Q(1);
Rin(3)<=Q(2);
Rout(2)<=Q(2);
Rin(2)<=Q(3);
Tempout<=Q(3);
Rout(1)<='0';
Rin(1)<='0';



else

Rin(1)<=Q(1);
Rout(1)<=Q(1);
Rin(2)<=Q(2);
Rout(2)<=Q(2);
Rin(3)<=Q(3);
Rout(3)<=Q(3);
Tempin<='0';
Tempout<='0';

end if;

end process selection;

Done<=Q(3);
Deneme(2)<=Q(1);
Deneme(1)<=Q(2);
Deneme(0)<=Q(3);

loadtobus:process(Extern,Rout,Tempout,w)

begin
if Extern='1' then
Buswires<=Data;
elsif Rout(1)='1' then
Buswires<=R1;
elsif Rout(2)='1' then
Buswires<=R2;
elsif Rout(3)='1' then
Buswires<=R3;
elsif Tempout='1' then
Buswires<=Temp;
else
Buswires<=(OTHERS=>'Z');
end if;
end process loadtobus;

loadtoregister:process(Rin,Tempin,Clock)
begin
if Rin(1)='1' then
R1<=Buswires;
elsif Rin(2)='1' then
R2<=Buswires;
elsif Rin(3)='1' then
R3<=Buswires;
elsif Tempin='1' then
Temp<=Buswires;
end if;
end process loadtoregister;


--firstdatain:TRIS generic map(N=>M)
-- port map(Data,Extern,Buswires);
--
--register1:registern generic map(N=>M)
-- port map(Buswires,Rin(1),Clock,R1);
--
--register2:registern generic map(N=>M)
-- port map(Buswires,Rin(2),Clock,R2);
--
--register3:registern generic map(N=>M)
-- port map(Buswires,Rin(3),Clock,R3);
--
--registertemp:registern generic map(N=>M)
-- port map(Buswires,Tempin,Clock,Temp);
--
--trist1:TRIS generic map(N=>M)
-- port map(R1,Rout(1),Buswires);
--
--trist2:TRIS generic map(N=>M)
-- port map(R2,Rout(2),Buswires);
--
--trist3:TRIS generic map(N=>M)
-- port map(R3,Rout(3),Buswires);
--
--tristemp:TRIS generic map(N=>M)
-- port map(Temp,Tempout,Buswires);


end Behavioral;

And This my Shift register(3 bit shift register to sends enable Rins and 
Routs)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CntrlCrt is
generic(K:integer:=4);
Port ( Resetn,Clock: in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (1 to K):="000");
end CntrlCrt;

architecture Behavioral of CntrlCrt is
signal counter1 :STD_LOGIC_VECTOR(1 downto 0):="00";
signal s:STD_LOGIC:='1';
begin

process(Clock,Resetn)
begin

if Resetn = '1' then
Q<=(OTHERS=>'0');
counter1<="10";
elsif Clock'EVENT and Clock ='1' then

if counter1="10" then
counter1<="00";
s<='1';
else
counter1<=counter1+1;
s<='0';
end if;

shftbits:For i in 1 to K-1 loop
Q(i)<=Q(i+1);
end loop;
Q(K)<=s;

end if;
end process;

end Behavioral;

Everything is wrote by me please do not copy without obtaining 
permission.