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Forum: FPGA, VHDL & Verilog Can't assign value in the register


Author: Loly Yoshi (Company: loly) (lolyoshi)
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Hi all, I need your help.

This stage includes two 8-to-1 multiplexers, one 9-
bit integer adder, one 1-to-8 demultiplexer, and an
internal register bank. Inputs X0-X4 and X7 are connected
directly to output registers. Inputs X5 and X6 are shifted
with predefined values and are stored in the internal
register bank. The multiplexers select values from the
register bank and feed them into the inputs of the adder.
The demultiplexer distributes output from the adder to
the output registers Y5 and Y6 or send them back to the
register file. The last two cycles are don’t care.

I attach the architecture, the truth table and the simulation of this 
stage

This is my code
module Stage2(CLK, Resetn, x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7);
  input CLK, Resetn;
  input [7:0]x0, x1, x2, x3, x4, x5, x6, x7;
  output [7:0]y0, y1, y2, y3, y4, y5, y6, y7;
  wire inputEnable;
  wire [2:0]S;
  wire [5:0]Rout ;
  wire [7:0]Rx5, Rx6, outMux1, outMux2, Y, R0, R1, R2, R3;
  
  assign inputEnable = &S; 
  Regn Rgx5(x5, inputEnable, CLK, Rx5); 
  Regn Rgx6(x6, inputEnable, CLK, Rx6); 
  assign y0 = x0;
  assign y1 = x1;
  assign y2 = x2;
  assign y3 = x3;
  assign y4 = x4;
  assign y7 = x7;
  Counter counter(CLK, 1, Resetn, S);
  Multi1 Mux1(Rx5, R0, Rx5, Rx6, R3, Rx6, S[2:0], outMux1);
  Multi2 Mux2(Rx5, Rx5, Rx5, Rx6, R1, R2, S[2:0], outMux2);
  ALU alu(outMux1, outMux2, S[2], Y);
  Decode Dec(S[2:0], Rout);
  Regn RgR0(Y, Rout[0], CLK, R0);
  Regn RgR1(Y, Rout[1], CLK, R1);
  Regn RgR2(Y, Rout[2], CLK, R2);
  Regn RgR3(Y, Rout[3], CLK, R3);
  Regn Ry5(Y, Rout[4], CLK, y5);
  Regn Ry6(Y, Rout[5], CLK, y6);
  
endmodule

module Multi1(R0, R1, R2, R3, R4, R5, sel, bus);
  input [2:0]sel;
  input [7:0]R0, R1, R2, R3, R4, R5;
  output reg[7:0]bus;
  
  always @(sel)
  begin
    case(sel)
      3'b000:    bus <= R0>>2;
      3'b010:    bus <= R1;
      3'b011:    bus <= R2>>2;
      3'b100:    bus <= R3>>1;
      3'b101:    bus <= R4;
      3'b110:    bus <= R5;
      default:  bus <= 8'bxxxxxxxx;
    endcase
  end  

endmodule

module Multi2(R0, R1, R2, R3, R4, R5, sel, bus);
  input [2:0]sel;
  input [7:0]R0, R1, R2, R3, R4, R5;
  output reg[7:0]bus;

  always @(sel)
  begin
    case(sel)
      3'b000:    bus <= 6>>R0;
      3'b001:    bus <= (R1<<5)>>6;
      3'b010:    bus <= R2>>3;
      3'b011:    bus <= R3>>3;
      3'b100:    bus <= R4;
      3'b101:    bus <= R5;
      default:  bus <= 8'bxxxxxxxx;
    endcase
  end

endmodule

module Counter(CLK, Enable, Resetn, S);
  input CLK, Enable, Resetn;
  output reg [2:0]S;
  
  always @(posedge CLK)
    begin
      if(Resetn == 0)
        S <= 3'b111;
      else
      begin
        if (Enable == 1)
          S <= S + 1;
      end
    end

endmodule

module Regn(R, Rin, CLK, Q);
  input [7:0]R;
  input Rin, CLK;
  output reg [7:0]Q;
  
  always @(posedge CLK)
    begin
      if(Rin)
        Q <= R;
      else
        Q <= Q;
    end
  
endmodule

module ALU(a, b, sel, x);
  input sel;
  input [7:0]a, b;  
  output [7:0]x;

  assign x = sel? a-b:a+b;

endmodule

module Decode(sel, Rout);
  input [2:0]sel;
  output reg[5:0]Rout;
  
  always @(sel)
  begin
    case(sel)
      3'b000:    Rout <= 6'b000001;
      3'b001:    Rout <= 6'b000010;
      3'b010:    Rout <= 6'b000100;
      3'b011:    Rout <= 6'b001000;
      3'b100:    Rout <= 6'b010000;
      3'b101:    Rout <= 6'b100000;
      default:  Rout <= 6'b000000;
    endcase
  end

endmodule

My problem is when it calculates the value in Y. It can't assign in R0, 
R1, R2, R3 as I expected

Thank for your help

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