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Forum: FPGA, VHDL & Verilog Can't assign value in the register


Can't assign value in the register
von Loly Y. (Company: loly) (lolyoshi)

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Hi all, I need your help.

This stage includes two 8-to-1 multiplexers, one 9-
bit integer adder, one 1-to-8 demultiplexer, and an
internal register bank. Inputs X0-X4 and X7 are connected
directly to output registers. Inputs X5 and X6 are shifted
with predefined values and are stored in the internal
register bank. The multiplexers select values from the
register bank and feed them into the inputs of the adder.
The demultiplexer distributes output from the adder to
the output registers Y5 and Y6 or send them back to the
register file. The last two cycles are don’t care.

I attach the architecture, the truth table and the simulation of this 
stage

This is my code
1
module Stage2(CLK, Resetn, x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7);

2
  input CLK, Resetn;

3
  input [7:0]x0, x1, x2, x3, x4, x5, x6, x7;

4
  output [7:0]y0, y1, y2, y3, y4, y5, y6, y7;

5
  wire inputEnable;

6
  wire [2:0]S;

7
  wire [5:0]Rout ;

8
  wire [7:0]Rx5, Rx6, outMux1, outMux2, Y, R0, R1, R2, R3;

9
  

10
  assign inputEnable = &S; 

11
  Regn Rgx5(x5, inputEnable, CLK, Rx5); 

12
  Regn Rgx6(x6, inputEnable, CLK, Rx6); 

13
  assign y0 = x0;

14
  assign y1 = x1;

15
  assign y2 = x2;

16
  assign y3 = x3;

17
  assign y4 = x4;

18
  assign y7 = x7;

19
  Counter counter(CLK, 1, Resetn, S);

20
  Multi1 Mux1(Rx5, R0, Rx5, Rx6, R3, Rx6, S[2:0], outMux1);

21
  Multi2 Mux2(Rx5, Rx5, Rx5, Rx6, R1, R2, S[2:0], outMux2);

22
  ALU alu(outMux1, outMux2, S[2], Y);

23
  Decode Dec(S[2:0], Rout);

24
  Regn RgR0(Y, Rout[0], CLK, R0);

25
  Regn RgR1(Y, Rout[1], CLK, R1);

26
  Regn RgR2(Y, Rout[2], CLK, R2);

27
  Regn RgR3(Y, Rout[3], CLK, R3);

28
  Regn Ry5(Y, Rout[4], CLK, y5);

29
  Regn Ry6(Y, Rout[5], CLK, y6);

30
  

31
endmodule

32
33
module Multi1(R0, R1, R2, R3, R4, R5, sel, bus);

34
  input [2:0]sel;

35
  input [7:0]R0, R1, R2, R3, R4, R5;

36
  output reg[7:0]bus;

37
  

38
  always @(sel)

39
  begin

40
    case(sel)

41
      3'b000:    bus <= R0>>2;

42
      3'b010:    bus <= R1;

43
      3'b011:    bus <= R2>>2;

44
      3'b100:    bus <= R3>>1;

45
      3'b101:    bus <= R4;

46
      3'b110:    bus <= R5;

47
      default:  bus <= 8'bxxxxxxxx;

48
    endcase

49
  end  

50
51
endmodule

52
53
module Multi2(R0, R1, R2, R3, R4, R5, sel, bus);

54
  input [2:0]sel;

55
  input [7:0]R0, R1, R2, R3, R4, R5;

56
  output reg[7:0]bus;

57
58
  always @(sel)

59
  begin

60
    case(sel)

61
      3'b000:    bus <= 6>>R0;

62
      3'b001:    bus <= (R1<<5)>>6;

63
      3'b010:    bus <= R2>>3;

64
      3'b011:    bus <= R3>>3;

65
      3'b100:    bus <= R4;

66
      3'b101:    bus <= R5;

67
      default:  bus <= 8'bxxxxxxxx;

68
    endcase

69
  end

70
71
endmodule

72
73
module Counter(CLK, Enable, Resetn, S);

74
  input CLK, Enable, Resetn;

75
  output reg [2:0]S;

76
  

77
  always @(posedge CLK)

78
    begin

79
      if(Resetn == 0)

80
        S <= 3'b111;

81
      else

82
      begin

83
        if (Enable == 1)

84
          S <= S + 1;

85
      end

86
    end

87
88
endmodule

89
90
module Regn(R, Rin, CLK, Q);

91
  input [7:0]R;

92
  input Rin, CLK;

93
  output reg [7:0]Q;

94
  

95
  always @(posedge CLK)

96
    begin

97
      if(Rin)

98
        Q <= R;

99
      else

100
        Q <= Q;

101
    end

102
  

103
endmodule

104
105
module ALU(a, b, sel, x);

106
  input sel;

107
  input [7:0]a, b;  

108
  output [7:0]x;

109
110
  assign x = sel? a-b:a+b;

111
112
endmodule

113
114
module Decode(sel, Rout);

115
  input [2:0]sel;

116
  output reg[5:0]Rout;

117
  

118
  always @(sel)

119
  begin

120
    case(sel)

121
      3'b000:    Rout <= 6'b000001;

122
      3'b001:    Rout <= 6'b000010;

123
      3'b010:    Rout <= 6'b000100;

124
      3'b011:    Rout <= 6'b001000;

125
      3'b100:    Rout <= 6'b010000;

126
      3'b101:    Rout <= 6'b100000;

127
      default:  Rout <= 6'b000000;

128
    endcase

129
  end

130
131
endmodule


My problem is when it calculates the value in Y. It can't assign in R0, 
R1, R2, R3 as I expected

Thank for your help

  


  




  

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