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Forum: FPGA, VHDL & Verilog User Constraints File


Author: John Smith (samit_basak)
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What dose it mean by User Constraints File?
I wrote the following program for seven segment display driver using 
Xilinx CoolRunner starter kit-
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY seg7 IS
PORT (D       : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
      S       : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END seg7;
ARCHITECTURE display OF SEG7 IS
BEGIN
s <=  "1000000" WHEN d = "0000" ELSE -- H"40"
      "1111001" WHEN d = "0001" ELSE -- H"79"
      "0100100" WHEN d = "0010" ELSE -- H"24"
      "0110000" WHEN d = "0011" ELSE -- H"30"
      "0011001" WHEN d = "0100" ELSE -- H"19"
      "0010010" WHEN d = "0101" ELSE -- H"12"
      "0000010" WHEN d = "0110" ELSE -- H"02"
      "1111000" WHEN d = "0111" ELSE -- H"78"
      "0000000" WHEN d = "1000" ELSE -- H"00"
      "0010000" WHEN d = "1001" ELSE -- H"10"
      "0001000" WHEN d = "1010" ELSE -- H"08"
      "0000011" WHEN d = "1011" ELSE -- H"03"
      "1000110" WHEN d = "1100" ELSE -- H"46"
      "0100001" WHEN d = "1101" ELSE -- H"21"
      "0000110" WHEN d = "1110" ELSE -- H"06"
      "0001110";                     -- H"0E"
END display;

But what will be the User Constraints File for it?

Author: na sowas (Guest)
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In the User Constraints File you e.g. assign pins to your top entity 
port and in this file you specify a desired clock rate.

BTW:
s <=  "1000000" WHEN d = "0000" ELSE -- H"40"
      "1111001" WHEN d = "0001" ELSE -- H"79"
      "0100100" WHEN d = "0010" ELSE -- H"24"
      :
this you could write a little more readable:
s <=  x"40" WHEN d = x"0" ELSE 
      x"79" WHEN d = x"1" ELSE 
      x"24" WHEN d = x"2" ELSE 
      :
      x"06" WHEN d = x"E" ELSE 
      x"0E"

Author: John Smith (samit_basak)
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Thanks...
But the problem is that after implementing this code it created a .JED 
file for the CoolRunner II but nothing was happening.Then I realized 
that I have to make an .UCF file for that project.But I really don't 
know how to make one for my program.So can u plz advice what shall I 
do??

Author: na sowas (Guest)
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> But I really don't know how to make one for my program.
> So can u plz advice what shall I do??
Go to the Processes and click on Assign Package Pins. Then you will be 
asked to add a ucf file to your design. And after starting the Wizzard 
(PACE) you can assign the pins simply by Drag&Drop.

Author: John Smith (samit_basak)
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Thnx...
I would like to know how can I give an audible output?Like if sum1 has 
pressed the push button on the Xilinx CPLD starter kit,so there shud b 
an audible output...
If possible I need ur suggestion?And thank u again...

Author: na sowas (Guest)
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> If possible I need ur suggestion?And thank u again...
What kind of speaker do you have?

Usually thats the way:
Generate a audible frequency with a counter. Connect it to the speaker 
pins. When the button is not pressed reset the counter, so theres 
nothing to hear...
:
use ieee.numeric_std.all
:
  port ( clk : in std_logic;
         btn : in std_logic;
         spkr : out std_logic);
:
 signal counter : integer range 0 to 10_000_000/1600 := 0; -- clk-frequency = 10Mhz, speaker output = 800Hz
 signal intspkr : std_logic := '0';
:
 process begin
    wait until rising_edge(clk);
    if (counter<10_000_000/1600) then -- reached end of counter?
       counter <= counter+1;          -- no:  increment  
    else 
       counter <= 0;                  -- yes: reset counter
       intspkr <= not intspkr;        --      toggle output
    end if;
    if (btn='0') then  -- button not pressed:  
       counter <= 0;   -- reset counter
    end if;
 end process;
 spkr <= intspkr;
:

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