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Forum: FPGA, VHDL & Verilog ERROR:ConstraintSystem:59


Author: Michael Milan (Company: Uni Hannover) (babybk)
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Hi everybody,

I've created a function block with

*Input:CLK and IO with 7 bits
(CLK for clock and IO for defination 7 SW in FPGA Spartan 3:from SW0 to 
SW6)
*Output:PMW1,PWM2,PWM3

And then i definate Floorplan IO and run Synthesize but have enrrors

ERROR:ConstraintSystem:59 - Constraint <NET "PWM1"  LOC = "N7" |>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "PWM2"  LOC = "T8" |>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "PWM3"  LOC = "R6" |>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<0>"  LOC = "F12" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<1>"  LOC = "G12" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<2>"  LOC = "H14" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<3>"  LOC = "H13" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<4>"  LOC = "J14" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<5>"  LOC = "J13" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<6>"  LOC = "K14" 
|>
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>


Please help me
Thanks you.

Author: Michael Milan (Company: Uni Hannover) (babybk)
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Beside exist too errors after i run file pwm_sc.ucf

"ERROR: the file pwm_sc.ngd is missing, the Constraints Editor can not 
be launched."

How can i fix these error?

Thanks you again

Author: Michael Milan (Company: Uni Hannover) (babybk)
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In addition
Here is details my errors

ERROR:ConstraintSystem:59 - Constraint <NET "PWM1"  LOC = "N7" |>
   [pwm_sc.ucf(5)]: NET "PWM1" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(5)]: NET "PWM1" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "PWM2"  LOC = "T8" |>
   [pwm_sc.ucf(6)]: NET "PWM2" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(6)]: NET "PWM2" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "PWM3"  LOC = "R6" |>
   [pwm_sc.ucf(7)]: NET "PWM3" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(7)]: NET "PWM3" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<0>"  LOC = "F12" 
|>
   [pwm_sc.ucf(8)]: NET "SchalterIO<0>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(8)]: NET "SchalterIO<0>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<1>"  LOC = "G12" 
|>
   [pwm_sc.ucf(9)]: NET "SchalterIO<1>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(9)]: NET "SchalterIO<1>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<2>"  LOC = "H14" 
|>
   [pwm_sc.ucf(10)]: NET "SchalterIO<2>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(10)]: NET "SchalterIO<2>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<3>"  LOC = "H13" 
|>
   [pwm_sc.ucf(11)]: NET "SchalterIO<3>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(11)]: NET "SchalterIO<3>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<4>"  LOC = "J14" 
|>
   [pwm_sc.ucf(12)]: NET "SchalterIO<4>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(12)]: NET "SchalterIO<4>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<5>"  LOC = "J13" 
|>
   [pwm_sc.ucf(13)]: NET "SchalterIO<5>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(13)]: NET "SchalterIO<5>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <NET "SchalterIO<6>"  LOC = "K14" 
|>
   [pwm_sc.ucf(14)]: NET "SchalterIO<6>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
   [pwm_sc.ucf(14)]: NET "SchalterIO<6>" not found.  Please verify that:
   1. The specified design element actually exists in the original 
design.
   2. The specified object is spelled correctly in the constraint source 
file.



I've maked "Cleanup Project files" in Tap Project but not success.

Author: Nephilim (Guest)
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please post the entity of your design and the constrains

Author: Klaus Falser (Guest)
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Maybe it's easier for you to discuss this in german?
http://www.mikrocontroller.net/forum/fpga-vhdl-cpld

The errors are saying mainly that these signals were not found.
Could be they were optimized away, since the compiler considered they as 
not used.
This can by an error in the description or maybe since your design is 
not complete yet.

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