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Forum: ARM programming with GCC/GNU tools AT91SAM7S256 SPI does not work


Author: Min Ge (minge519)
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Hi everyone,

I am trying to use AT91SAM7S256 SPI, butit does not work.
When I send data outof SPI port, I can not see any change on SPCK and
MOSI pins.

I use eclipse and SAM-ICE to debug on the AT91SAM7S-EK board.
I found when I read the SPI register in eclipse. All the register is 0.

The following are may SPI init code:

    AT91F_SPI_Reset     (AT91C_BASE_SPI);
    AT91F_SPI_Enable    (AT91C_BASE_SPI);
    AT91F_SPI_CfgMode   (AT91C_BASE_SPI, SPI_MSTR | SPI_FIX_SLCT |
SPI_CS_DIRECT | SPI_MODE_FAULT_DS | SPI_LOCAL_LOOP_DS | SPI_FIXED_CS_0);
    AT91F_SPI_CfgCs     (AT91C_BASE_SPI, 0, SPI_SCK_IDLE_LOW |
SPI_SCK_SAMPLE_RISING | SPI_CS_LOW_AFTR_TRANS | SPI_8_BITS_PER_TRANS |
(2*SPI_SCK_DIV_FACTOR));

    AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
    ((unsigned int) AT91C_PA13_MOSI    ) |
    ((unsigned int) AT91C_PA31_NPCS1   ) |
    ((unsigned int) AT91C_PA14_SPCK    ) |
    ((unsigned int) AT91C_PA11_NPCS0   ) |
    ((unsigned int) AT91C_PA12_MISO    ), // Peripheral A
//    ((unsigned int) AT91C_PA9_NPCS1   ) |
//    ((unsigned int) AT91C_PA22_NPCS3   ) |
//    ((unsigned int) AT91C_PA3_NPCS3   ) |
//    ((unsigned int) AT91C_PA5_NPCS3   ) |
//    ((unsigned int) AT91C_PA10_NPCS2   ) |
//    ((unsigned int) AT91C_PA30_NPCS2   )
        0 ); // Peripheral B

Thanks. I am looking forward to every reply.

Min Ge

Author: Andreas Schwarz (andreas) (Admin) Flattr this
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Min Ge wrote:
> Hi everyone,
>
> I am trying to use AT91SAM7S256 SPI, butit does not work.
> When I send data outof SPI port, I can not see any change on SPCK and
> MOSI pins.

See page 253 in the datasheet:

"The SPI may be clocked through the Power Management Controller (PMC),
thus the programmer must first configure the PMC to enable the SPI
clock. "

Author: Min Ge (minge519)
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Andreas S. wrote:
> Min Ge wrote:
>> Hi everyone,
>>
>> I am trying to use AT91SAM7S256 SPI, butit does not work.
>> When I send data outof SPI port, I can not see any change on SPCK and
>> MOSI pins.
>
> See page 253 in the datasheet:
>
> "The SPI may be clocked through the Power Management Controller (PMC),
> thus the programmer must first configure the PMC to enable the SPI
> clock. "

I got it . It is working now. Thanks a lot.

Min Ge

Author: Nick Moszer (moszer)
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Min Ge wrote:
> Andreas S. wrote:
>> Min Ge wrote:
>>> Hi everyone,
>>>
>>> I am trying to use AT91SAM7S256 SPI, butit does not work.
>>> When I send data outof SPI port, I can not see any change on SPCK and
>>> MOSI pins.
>>
>> See page 253 in the datasheet:
>>
>> "The SPI may be clocked through the Power Management Controller (PMC),
>> thus the programmer must first configure the PMC to enable the SPI
>> clock. "
>
> I got it . It is working now. Thanks a lot.
>
> Min Ge


I'm having a similar issue and (believe) I've followed the correct init
steps
After looking through the example and doc at
http://www.atmel.com/dyn/resources/prod_documents/...
I have:

// Reset the SPI controller
AT91F_SPI_Reset     (AT91C_BASE_SPI);

// Configure PMC by enabling SPI clock
AT91F_SPI_CfgPMC ();

// Setup the SPI Mode Register
AT91F_SPI_CfgMode   (AT91C_BASE_SPI, MASTER | SPI_FIX_SLCT |
SPI_CS_DIRECT |  SPI_MODE_FAULT_DS | SPI_LOCAL_LOOP_DS |
SPI_FIXED_CS_0);

// Setup the SPI Chip Select Register
AT91F_SPI_CfgCs     (AT91C_BASE_SPI, 0, SPI_SCK_IDLE_LOW |
SPI_SCK_SAMPLE_RISING | SPI_CS_LOW_AFTR_TRANS | SPI_8_BITS_PER_TRANS |
(2*SPI_SCK_DIV_FACTOR));

// Setup the SPI Bus Pins
AT91F_SPI_CfgPIO ();

// Enable the SPI Bus
AT91F_SPI_Enable (AT91C_BASE_SPI);

My defines are as follows:

#define SPI_FIX_SLCT            0   //Fixed Peripheral Select
#define SPI_CS_DIRECT      0   //Chip Select is directly connected
#define SPI_MODE_FAULT_DS    0   //Mode Fault Enabled
#define SPI_LOCAL_LOOP_DS    0   //Loop back disabled
#define SPI_FIXED_CS_0      0   //PCS = xxx0
#define SPI_SCK_IDLE_LOW    0   //CS idles low
#define SPI_SCK_SAMPLE_RISING    0   //Data is changed on the leading
edge of SPCK and captured on the following edge of SPCK.

#define SPI_CS_LOW_AFTR_TRANS    0   //The Peripheral Chip Select Line
rises as soon as the last transfer is achieved.

#define SPI_8_BITS_PER_TRANS    0  //8bit transfers
#define SPI_SCK_DIV_FACTOR    0x00003200

This is also on a AT91SAM7S256.

When I send data by writing to the SPI_TDR register the CS line never
goes low.  I checked the status register and it says the SPI bus is
enabled.  Anyone have any thoughts?  Any and all help is appreciated.

Author: Martin Thomas (Guest)
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Maybe you can find some hints in my AT91-SPI interface for the Embedded
Filesystem Library (efsl) files src/interface/at91_spi.c) at
http://www.siwawi.arubi.uni-kl.de/avr_projects/arm...
download the latest beta-version marked with [T4].

Martin Thomas

Author: Przemyslaw Grzesiowski (pgp)
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in my opinion it should be :

AT91F_SPI_CfgMode   (AT91C_BASE_SPI, AT91C_SPI_MSTR | SPI_FIX_SLCT<<1 |
SPI_CS_DIRECT<<2 | SPI_MODE_FAULT_DS<<4 | SPI_LOCAL_LOOP_DS<<7 |
SPI_FIXED_CS_0<<16 );


Don't forget to use Bitwise Operators !

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