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Forum: ARM programming with GCC/GNU tools LPC2106 Capture Interrupts


Author: Gerard Sequeira (bluehash)
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Hello,

I'm capturing edge(positive and negative) interrupts on the capture
pin(CAP1.3).
My code works well at times but resets the processor very frequently.
My platform is an arm-elf-gcc (4.1.1) on Fedora 6.
Since arm-elf-gcc does not allow interrupts in THUMB mode, I used ARM
with -mthumb-interwork

My capture interrupt routine:

//Capture1.3/1.2 interrupt initialization

void captureISR_init(void){

        PINSEL1 |= 0x10;    //connect CAP1.3 to P0.18
        T1CCR   |= 0x0E00;  //interrupt on rising/falling edge CAP1.3

        VICVectAddr0 = (unsigned)captureISR;  //set the capture vector
address
        VICVectCntl0 =  0x20 | 5;
        VICIntEnable =  0x0000020;              //enable Timer1
interrupt
}

void _attribute_ ((interrupt("IRQ"))) captureISR(void){

        count_int++;
        count_int_poll++;

        T1IR |=         0x80;        //clear T1 CAP1.2 and CAP1.3
interrupt
        VICVectAddr =   0x00000000;   //Dummy write to signal end of
interrupt
        ISR_EXIT();
}

Doing a bit of research showed that THUMB mode has a thing with
interrupts.
I tried using code from Martin Thomas from here
http://gandalf.arubi.uni-kl.de/avr_projects/arm_projects/
(LPC2106, LPC2129, LPC2138 and LPC2378 ARM7 interrupt-driven UART)

My routine is now with ISR_ENTRY and ISR_EXIT:
void __attribute__((naked)) captureISR(void){

        ISR_ENTRY();
        count_int++;
        count_int_poll++;

        T1IR |= 0x80;        //clear T1 CAP1.2 and CAP1.3 interrupt
        VICVectAddr =   0x00000000;   //Dummy write to signal end of
interrupt
        ISR_EXIT();
}


I copied armVIC.c armVIC.h and crt0.S into my working directory.

On compiling with THUMB mode, I get these errors:
/tmp/ccqbN0BB.s: Assembler messages:
/tmp/ccqbN0BB.s:715: Error: lo register required -- `sub lr,lr,#4'
/tmp/ccqbN0BB.s:716: Error: selected processor does not support `stmfd
sp!,{r0-r12,lr}'
/tmp/ccqbN0BB.s:717: Error: selected processor does not support `mrs
r1,spsr'
/tmp/ccqbN0BB.s:718: Error: selected processor does not support `stmfd
sp!,{r1}'
/tmp/ccqbN0BB.s:743: Error: lo register required -- `ldmfd sp!,{r1}'
/tmp/ccqbN0BB.s:744: Error: selected processor does not support `msr
spsr_c,r1'
/tmp/ccqbN0BB.s:745: Error: Thumb load/store multiple does not support
{reglist}^ -- `ldmfd sp!,{r0-r12,pc}^'
make: *** [utils.o] Error 1


On compiling in ARM mode with -mthumb-interwork, I get these errors:
crt0.o: In function `_reset':
crt0.S:166: undefined reference to `_stack'
collect2: ld returned 1 exit status
make: *** [srv1.hex] Error 1

Is there a file I'm missing out?

Regards,
Gerard









/tmp/ccqSEsF4.s: Assembler messages:
/tmp/ccqSEsF4.s:715: Error: lo register required -- `sub lr,lr,#4'
/tmp/ccqSEsF4.s:716: Error: selected processor does not support `stmfd
sp!,{r0-r12,lr}'
/tmp/ccqSEsF4.s:717: Error: selected processor does not support `mrs
r1,spsr'
/tmp/ccqSEsF4.s:718: Error: selected processor does not support `stmfd
sp!,{r1}'
/tmp/ccqSEsF4.s:743: Error: lo register required -- `ldmfd sp!,{r1}'
/tmp/ccqSEsF4.s:744: Error: selected processor does not support `msr
spsr_c,r1'
/tmp/ccqSEsF4.s:745: Error: Thumb load/store multiple does not support
{reglist}^ -- `ldmfd sp!,{r0-r12,pc}^'
make: *** [utils.o] Error 1

Author: Martin Thomas (mthomas) (Moderator)
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Gerard Sequeira wrote:
> I copied armVIC.c armVIC.h and crt0.S into my working directory.

I suggest to copy the linker-script too.

> On compiling with THUMB mode, I get these errors:
> /tmp/ccqbN0BB.s: Assembler messages:
> /tmp/ccqbN0BB.s:715: Error: lo register required -- `sub lr,lr,#4'
> ...

Yes, the macros expand to some inline assembler instructions which are
for ARM mode only so the code has to be compiled in ARM-mode.

> On compiling in ARM mode with -mthumb-interwork, I get these errors:
> crt0.o: In function `_reset':
> crt0.S:166: undefined reference to `_stack'
> collect2: ld returned 1 exit status
> make: *** [srv1.hex] Error 1
>
> Is there a file I'm missing out?

Maybe your "old" linker-script just does not provide the needed
information (address of _stack). Try to compare your linker-script with
the linker-script from my example or just try to use the script from the
example.


Martin Thomas

Author: Gerard Sequeira (bluehash)
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Thank you so much for your reply.

That got rid of the errors.
Since I'm  loading into RAM,I get a warning:cannot find entry symbol
_start

arm-elf-gcc main.o uart0.o uart1.o iap.o armVIC.o utils.o
startup/libea_startup_thumb.a  -I./startup -mcpu=arm7tdmi
-mthumb-interwork -nostartfiles -T build_files/LPC2106_RAM.ld -o
srv1.elf -Wl,-Map=srv1.map,--cref
/opt/arm-elf-tools/gcc-4.1.1/lib/gcc/arm-elf/4.1.1/../../../../arm-elf/b 
in/ld:
warning: cannot find entry symbol _start; defaulting to 40000000


Though I can copy my hex file, my program wont start, maybe because of
no _start?

Author: Martin Thomas (mthomas) (Moderator)
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Gerard Sequeira wrote:
> Thank you so much for your reply.
>
> That got rid of the errors.
> Since I'm  loading into RAM,I get a warning:cannot find entry symbol
> _start
>
> arm-elf-gcc main.o uart0.o uart1.o iap.o armVIC.o utils.o
> startup/libea_startup_thumb.a  -I./startup -mcpu=arm7tdmi
> -mthumb-interwork -nostartfiles -T build_files/LPC2106_RAM.ld -o
> srv1.elf -Wl,-Map=srv1.map,--cref
> /opt/arm-elf-tools/gcc-4.1.1/lib/gcc/arm-elf/4.1.1/../../../../arm-elf/b in/ld:
> warning: cannot find entry symbol _start; defaulting to 40000000
>
>
> Though I can copy my hex file, my program wont start, maybe because of
> no _start?

To get rid of the warning add a label in the startup-code just above the
reset-vector "ldr pc".
Since you are "loading into RAM": Are the interrupt-vectors in place?
Remapping set correclty? Does the programming software set the PC to the
start-address (usualy the reset-vector execption address)? When using
ISP: check the user-manual the bootloader uses some bytes in RAM, so
maybe user-data gets overwritten. Difficult to help without knowing the
code (what is "libea_startup_thumb.a"?). You may create a minimal
example to reproduce the problem (full code, linker-script, makefile)
pack it and place it on a server than post the URL here.

Author: Gerard Sequeira (bluehash)
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I managed to compile everything.
As in your example the ISR entry and exit assembly stubs are inserted.
However the processor still resets at times.
Compiled with ARM (no interwork)

Is this the same way the following problem was solved?
http://en.mikrocontroller.net/topic/102252#224743

My routine:
/*Capture1.3/1.2 interrupt*/
void _attribute_ ((interrupt(naked))) captureISR(void){


        asm("sub lr, lr,#4");
        asm("stmfd sp!, {r0-r12, lr}");
        asm("mrs r1, spsr");
        asm("stmfd sp!, {r1}");

        count_int++;
        count_int_poll++;
        //unsigned int x=(PI*DIAMETER*count_int_poll)/TICK;
        //printNumber(10, 8, FALSE, ' ', x);

        T1IR |=         0x80;//|0x40;        //clear T1 CAP1.2 and
CAP1.3 interrupt
        VICVectAddr =   0x00000000;       //Dummy write to signal end of
interrupt
        asm("ldmfd sp!,{r1}");
        asm("msr spsr_c,r1");
        asm("ldmfd sp!,{r0-r12,pc}^");
}

Author: Martin Thomas (mthomas) (Moderator)
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Please define "still resets at times". Maybe you see "spurious"
interrupts which would be not that unusual when using external capture
and a high frequency input signal. Is there an ISR which manages
"unvectored" interrupts (ISR at the VIS's default vector address)? Is
this ISR called? For a test increase a volatile counter in the default
ISR, clear the interrupt in the ISR and check the counter in main-loop.

Just a side-note: I suggest to keep the assembler instructions for a
sequence in a single asm volatile. There are tested macros for this see
i.e. the macros in armVIC.h (created by Bill Knight and included in some
of the examples in WinARM or from my Web-pages).

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