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Forum: ARM programming with GCC/GNU tools Problem while enabling Data cache


Author: MIthun (Guest)
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Hi all,
I want to enable I cache and data cachein arm922t.I enabled the I cache
by setting the control bit in cp15.But the code hangs while enabling D
cache.Iam running the code in system mode. The code i used is given
below.Can anybody help me..

         MRC     p15, 0, r0, c1, c0, 0       @ read CP15 register 1 into
r0
         BIC     r0, r0, #0x1                @ clear bit 0
         MCR     p15, 0, r0, c1, c0, 0       @ write value back

@Initialization instruction cache
@
@       MRC     p15, 0, r0, c1, c0, 0       @ read CP15 register 1 into
r0
@       ORR     r0, r0, #0xc0000000         @ set asynchronous clocking
mode
@       ORR     r0, r0, #0x1000             @ enable I cache
@       MCR     p15, 0, r0, c1, c0, 0       @ write back r0 into CP15
register 1

init_ttb

        MOV     r0,#0x28000     @ set start of Translation Table base
(16k Boundary)
        MCR     p15, 0, r0, c2, c0, 0       @ write to CP15 register 2

@ Create translation table for flat mapping
@ Top 12 bits of VA is pointer into table
@ Create 4096 entries from 000xxxxx to fffxxxxx

        LDR     r1,=0xfff                        @ loop counter
        MOV     r2,#2_110000000000          @ set access permissions
(AP) for full access SVC/USR (11:10)
        ORR     r2,r2,#2_000111100000       @ set for domain 15 (8:5)
        ORR     r2,r2,#2_000000010000       @ must be 1 (4)
        ORR     r2,r2,#2_000000000000       @ set non cachable non
bufferable (CB) (3:2)
        ORR     r2,r2,#2_000000000010       @ set for 1Mb section (1:0)
@
init_ttb_1
        ORR     r3,r2,r1,lsl#20             @ use loop counter to create
individual table entries
        STR     r3,[r0,r1,lsl#2]            @ str r3 at TTB base +
loopcount*4
        SUBS    r1,r1,#1                    @ decrement loop counter
        BPL     init_ttb_1
@
        ORR     r3,r3,#2_1100               @ set cachable and
bufferable attributes for section 0 (3:2)
        STR     r3,[r0]                     @ ie lower 1MB - this will
set cache to Write Back mode
@
@init_domains
        MOV     r0,#(2_01 << 30)            @ must define behaviour for
domain 15 (31:30), set client
        MCR     p15, 0, r0, c3, c0, 0       @ write to CP15 register 5

@
@ set global core configurations
@
        MRC     p15, 0, r0, c1, c0, 0       @ read CP15 register 1 into
r0

        ORR     r0, r0, #(0x1 <<12)         @ enable I Cache
        ORR     r0, r0, #(0x1 <<2)          @ enable D Cache
        ORR     r0, r0, #(2_11 <<30)        @ enable asynchronous
clocking mode
        ORR     r0, r0, #0x1                @ enable MMU

@
@ additional configuration options
@
@       ORR     r0, r0, #(0x1 <<14)         @ enable Round Robin cache
replacement
@       ORR     r0, r0, #(0x1 <<13)         @ enable Hi Vectors
@       ORR     r0, r0, #(0x1 <<1)          @ enable data address
alignment checking

        MCR     p15, 0, r0, c1, c0, 0       @ write cp15 register 1

        MOV   pc,lr                         @ return

        .end
Thanks in advance
Mithun

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