Forum: ARM programming with GCC/GNU tools Learning Make

Author: R.Swaving (Guest)
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I am learning to use make and trying to write my own make files. I got
the following problem: I got one test.c file in my root directory.
All is working fine when I use objects = test.o. However when I use the
string assignments it is not working anymore the following appears
test.o : no such file or directory. Is it possible to print the contents
of the used variables?
remark I used the windows gcc but my aim is to write make files for


#setting of compiler and target
cc = gcc


#files to be compiled
objects = test.o
root= ./
srcdir = $(root)
sourcefiles = $(foreach dir , $(srcdir), $(wildcard $(dir) /*.c))
#objects = $(notdir $(patsubst %.c, %.o, $(sourcefiles) ))

#linking object files
test  : $(objects)
    $(cc) -o test test.o

#compiling source files
test.o : test.c
    $(cc) -c test.c

.PHONY : clean
clean :
    del test *.o test.exe

#end of makefile

Author: Fordp (Guest)
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This is not really the right place for general make file questions.

You can output variables using the echo command

@echo "$(sourcefiles)"

All the best.


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