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Forum: ARM programming with GCC/GNU tools Instruction running cycle


Author: Min Ge (minge519)
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Hi all,

I want to build a hardware delay function usec or msec level.
Where can I get the instruction running cycle for me to calculate delay
code running time?

Thanks.

Min Ge

Author: Stefan (Guest)
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Often the instruction command set documentation from the µC manufacturer
has information about how many cycles a certain instruction requires.

Last time i wrote such delay functions, i used a more practical way.
Toogle a port before or after a delay loop and measure the resulting
frequency e.g. with a frequency counter or an oszilloscope when you loop
the delay loop.

while(1)
{
  my_toggle_port();
  my_delay_us(123);
}

Stefan

Author: Clifford Slocombe (clifford)
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Min Ge wrote:
> Hi all,
>
> I want to build a hardware delay function usec or msec level.
> Where can I get the instruction running cycle for me to calculate delay
> code running time?
>
> Thanks.
>
> Min Ge

I would not recommend that approach. Instruction cycles are variable
depending on the memory type, memory controller timing, whether caching
is enabled or not, and the clock controller settings. Since there are
many ARM based devices spanning the range from a few tens to hundreds of
MHz, and any number of memory types, as well as various cache sizes, the
code would not be easy to make portable.

Most (in fact I would suggest all) off-the-shelf ARM based
microcontrollers include  one or more programmable timers. Usually they
are called timer/counters, but often PWM, Real-time clock (RTC) and
watchdog timer modules can also be used as timers. These will provide
very accurate timing. You can either run one as a free tunning counter
and just poll it until it reaches a target, or you can use one to
generate time interval interrupts and increment a counter - this will
give you greater flexibility over resolution and range. You can of
course do even more sophisticated things with timers. If you use an
RTOS, timing services including delays are normally provided.

What controller are you using? And at what clock rate are you driving
it? That would enable anyone to provide you with more information. You
should also consult the chip's data sheet or user manual.

Clifford

Author: Min Ge (minge519)
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Clifford Slocombe wrote:
> Min Ge wrote:
>> Hi all,
>>
>> I want to build a hardware delay function usec or msec level.
>> Where can I get the instruction running cycle for me to calculate delay
>> code running time?
>>
>> Thanks.
>>
>> Min Ge
>
> I would not recommend that approach. Instruction cycles are variable
> depending on the memory type, memory controller timing, whether caching
> is enabled or not, and the clock controller settings. Since there are
> many ARM based devices spanning the range from a few tens to hundreds of
> MHz, and any number of memory types, as well as various cache sizes, the
> code would not be easy to make portable.
>
> Most (in fact I would suggest all) off-the-shelf ARM based
> microcontrollers include  one or more programmable timers. Usually they
> are called timer/counters, but often PWM, Real-time clock (RTC) and
> watchdog timer modules can also be used as timers. These will provide
> very accurate timing. You can either run one as a free tunning counter
> and just poll it until it reaches a target, or you can use one to
> generate time interval interrupts and increment a counter - this will
> give you greater flexibility over resolution and range. You can of
> course do even more sophisticated things with timers. If you use an
> RTOS, timing services including delays are normally provided.
>
> What controller are you using? And at what clock rate are you driving
> it? That would enable anyone to provide you with more information. You
> should also consult the chip's data sheet or user manual.
>
> Clifford


I use AT91SAM7S256.
I read the datasheet, it does not give the instruction running cycle.
I know timer can do the delay, but some times I just need usec level
(10us, or more short time ) I do not want to use timer, I do not care
the accuracy 5% is OK.
Thanks.

Min ge

Author: Dominic (Guest)
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Min Ge wrote:
> I use AT91SAM7S256.
> I read the datasheet, it does not give the instruction running cycle.
> I know timer can do the delay, but some times I just need usec level
> (10us, or more short time ) I do not want to use timer, I do not care
> the accuracy 5% is OK.
> Thanks.
>
> Min ge

The instruction cycle timing is explained in the TRM (technical
reference manual) of the ARM core your uC is using, in your case the
ARM7TDMI TRM: http://www.arm.com/pdfs/DDI0210C_7tdmi_r4p1_trm.pdf

If your code is running from SRAM, there are no wait-states, but if
you're running from Flash, there might be wait-states, depending on the
core frequency and flash speed.

Regards,

Dominic

Author: A.K. (Guest)
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Dominic wrote:

> if you're running from Flash, there might be wait-states, depending on the
> core frequency and flash speed.

...and on the exact code alignment, if it were a LPC2000.

I cannot recommend this approach, even though SAM7 does not apperar to
have alignment effects.

Either use a timer for the delay, or, if a timer cannot be used for some
reason, use a runtime calibrated delay loop: In initialization phase,
beyond memory system setup, use a timer to measure the runtime of the
delay loop with a defined loopcount. Calculate a multiplier which is
subsequently used to convert usec/msec values to loopcounts. ARMs have a
hardware multiplier making this approach feasible. But make sure you do
not have multiple copies of this delay look around.

Author: Clifford Slocombe (clifford)
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Min Ge wrote:
> I use AT91SAM7S256.
> I read the datasheet, it does not give the instruction running cycle.
> I know timer can do the delay, but some times I just need usec level
> (10us, or more short time ) I do not want to use timer, I do not care
> the accuracy 5% is OK.
> Thanks.
>
> Min ge

I did not suggest that the Atmel data sheet did describe the instruction
timing. The chip uses core processor technology from ARM. You need to
refer to the ARM documentation for that. The suggestion to consult the
data sheet was with respect to the preipherals that support timing
functionality.

I am not sure why you consider this approach as less appropriate or even
difficult, it is probably simpler than instruction cycle counting - you
will not have to write it in assembler for a start!

It is true that the AT91SAM7S devices are simple and have no cache or
external memory timing to worry about - but one day you may want your
code to run on a more sophisticated part (or even somthing other than an
ARM), so it is as well to make your code less dependent on system
timings you may have little control over.

Simply configure the timer as a free running high-frequency counter and
poll the counter until the required time has elapsed. The Timer/Counter
hardware can count at a frequesncy as fast as half the processor
frequency, while PWM counter can run at the processor frequency.

Clifford

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