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Messdiagramme einer AD5933 Impedanzmessung
AD5933 measurement (Rref=100000Ohm) calib raw signals real imag [LSB] [LSB] raw signals real imag [LSB] [LSB] phase phase[°] calib raw meas result f[Hz] impedance |Z| [Ohm] f[Hz]
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Diagramme einer AD5933 Impedanzmessung
AD5933 measurement (Rref=100000Ohm) calib raw signals real imag [LSB] f[Hz] raw signals [LSB] f[Hz] phase[°] calib raw meas result f[Hz] impedance [Z [Ohm] f[Hz]
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Diagramme einer AD5933 Messung
AD5933 measurement (Rref=100000Ohm) calib raw signals real imag [LSB] f[Hz] raw signals real imag [LSB] f[Hz] phase calib raw meas result phase[°] f[Hz] impedance [Z| Ohm] f[Hz]
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Tabellen und Text zum AD5933 Ausgangswiderstand
AD5933 output resistance depends on output voltage setup Table 5. Voltage Levels Respective Bias Levels for 3.3 V Table 10. Control Register Map (D10 to D9) Output Resistance 1 200 2 2.4k 3 1k 4 600 AD5933
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Schaltplan mit AD5933 IC und Header
H2 Header-Male-2.54_1x6 VOUT Vin SDA SCL R9 RFB Vin RFB VIN VOUT U4 AD5933WYRSZ-REEL7 NC SCL SDA AGND2 AGND1 DGND AVDD2 AVDD1 DVDD MCLK NC NC NC SCL SDA DGND +3.3V C3 0.1u C4 10u GND
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EVAL-AD5933EBZ Analog Devices Evaluation Board
ANALOG DEVICES EVAL-AD5933EBZ Rev. C 24.000. U5 CY7C68013A-56. LK1 LK2 LK3 LK4 LK5. C1 bis C35. R1 bis R15. T1 bis T6. J1. J6. VDD-EXT DGND. Power.
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Schaltplan eines Analog Front End Evaluation Boards
SCHEMATICS AND ARTWORK Analog Front End VDD RFB DNI R1 U1-B 7 5 R4 20K C2 C3 2 T2 C1 RK2 RK2 20K LK1 LK2 U2 AD5933BRSZ AGND DGND SCL 15 SCL CS 14 SDA SDA DOUT AGND_RFB 13 AGND_SIG 12 VDD VIN 4 RFB T7 6 VOUT AVDD_RFB 11 AVDD_SIG 10 N/G 8 EXT_CLK DVDS 7 EXT_OUT 3 CLK1 16MHz C10 0.1uF VDD GND 3 D/P C9 10uF C8 0.1uF VDD U1-A R7 C7 47nF R8 U1-C VDD C5 C6 0.1uF Figure 31. EVAL-AD5933EBZ USB Schematic
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Schaltplan eines Analog Front End Evaluation Boards
SCHEMATICS AND ARTWORK Analog Front End VDD RFB DNI R1 U1-B 7 5 R4 20K C2 C3 2 T2 C1 RK2 RK2 20K LK1 LK2 U2 AD5933BRSZ AGND DGND SCL 15 SCL CS 14 SDA SDA DOUT AGND_RFB 13 AGND_SIG 12 VDD VIN 4 RFB T7 6 VOUT AVDD_RFB 11 AVDD_SIG 10 N/G 8 EXT_CLK DVDS 7 EXT_OUT 3 CLK1 16MHz C10 0.1uF VDD GND 3 D/P C9 10uF C8 0.1uF VDD U1-A R7 C7 47nF R8 U1-C VDD C5 C6 0.1uF 10441-034 Figure 31. EVAL-AD5933EBZ USB Schematic
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Benutzeroberfläche einer Impedanzmesssoftware
AD5933 Beta Version REV1.0 Help:How to use software System clock External clock Internal oscillator Output Excitation Range1:2vp-p Range2:1vp-p Range 4:0.2vp-p Sweep Parameters Start Frequency (Hz) 30000
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Analog Devices EVAL-933EBZ Evaluation Board mit Messaufbau
ANALOG DEVICES EVAL-933EBZ Rev. C 24.000 R13 C14 C18 C26 C29 C12 C17 C20 R14 C21 C22 C27 C23 U5 C24 C26 C25 C33 C32 C36 C35 C31 C34 U2 R4 R5 R1 C2 T3 C1 R6 L2 Y2 T6 U4 J2 VDD_EXT DGND Power
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Tabelle mit Messwerten von Impedanz und Phasenlage
Impedance Magnitude Phase (rd) Phase (zd) LCR (rd) Degrees Z real Z imaginary 1kHz -1587 -1343 15644.8 576.906 0.085493 184.924532 392,18k 2kHz -96 -35 101.18 282.39 0.349607 200.013006 5kHz 315 401 153.08 5889.7 0.326681 358.122587 7kHz 439 239 239.008 17475.3 0.4794156 10kHz 315 401 22446.0 0.66236 3574.4497 11kHz 766 129 773.345 1.015536 0.017842 12kHz 832 135 942.81 10966.8 0.192648 15kHz 961 157 9059.61 0.17346 9.362456 17kHz 962 180 978.695 0.94213 34.8547 22kHz 1032 211 1053.35 0.201678 11.559232 25kHz 1391 322 1124.22 0.20831 11.937045 30kHz 1761 438 1291.53 0.226862 12.96313 35kHz 1929
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Elektronik-Messaufbau mit Breadboards und HP Test Fixture
ANALOG DEV EVAL- , 16047A TEST FIXTURE, HEWLETT PACKARD, LOW ±35V DC MAX HIGH
