library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

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-- Code d'un filtre recursif : Yn = Xn * C0 + Xn-1 * C1 + Xn-2 * C2 + Yn-1 * C3 + Yn-2 * C4 
-- !! Virgule fixe après les dix premiers bits de poids forts !!
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entity Filtre_IIR_38d_CoVa is
    generic(
        constant NB_Bit : integer := 38 + 9 -- X bit decimal + 10 bit signal
    );
    Port (
       Clk : in std_logic; -- Horloge (Fréquence d'échantillonage)
       Raz : in std_logic; -- Remise à zéro
       
       coeff_0 : in signed(NB_Bit downto 0); -- Coefficients
       coeff_1 : in signed(NB_Bit downto 0);
       coeff_2 : in signed(NB_Bit downto 0);
       coeff_3 : in signed(NB_Bit downto 0);
       coeff_4 : in signed(NB_Bit downto 0);
       
       Xn : in signed (9 downto 0); -- Signal d'entree 
       Yn : out signed (9 downto 0) -- Signal sortie
    );
end Filtre_IIR_38d_CoVa;

architecture Behavioral of Filtre_IIR_38d_CoVa is
                                 
    type delayed_signal_X_type is array(0 to 2) of signed (NB_Bit downto 0); 
    type delayed_signal_Y_type is array(0 to 1) of signed (NB_Bit downto 0); 
    
    -- Signaux Xn, Xn-1, Xn-2
    signal delayed_signal_X : delayed_signal_X_type;
   -- Signaux Yn-1, Yn-2
    signal delayed_signal_Y : delayed_signal_Y_type;
   -- Signal Yn
    signal Y_res : signed (NB_Bit*2+1 downto 0);
begin

    process (Clk)
    begin
        -- Initialisation 
        if Raz ='1' then 
            delayed_signal_X(0) <= (others => '0');
            delayed_signal_X(1) <= (others => '0');
            delayed_signal_X(2) <= (others => '0');
            delayed_signal_Y(0) <= (others => '0');
            delayed_signal_Y(1) <= (others => '0');
        elsif rising_edge (clk) then
            -- Entrée
            delayed_signal_X(0)(NB_Bit downto NB_Bit-9) <= Xn; 
            delayed_signal_X(0)(NB_Bit-10 downto 0) <= (others => '0'); 
            -- Buffer sortie Y
            delayed_signal_Y(0)<= Y_res (NB_Bit*2-9 downto NB_Bit-9);
            delayed_signal_Y(1) <= delayed_signal_Y(0);   
            -- Buffer Entrée X
            for i in 1 to 2 loop 
                delayed_signal_X(i) <= delayed_signal_X(i-1);    
            end loop;                   
        end if;   
    end process;
    
    Y_res <= (delayed_signal_X(0) * coeff_0) +
             (delayed_signal_X(1) * coeff_1) +
             (delayed_signal_X(2) * coeff_2) +
             (delayed_signal_Y(0) * coeff_3) +
             (delayed_signal_Y(1) * coeff_4);
             
    -- Signal de Sortie (sans virgule)
    Yn <= delayed_signal_Y(0)(NB_Bit downto NB_Bit-9);
    
end Behavioral;