library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mavg is
    generic (
        MAX_MAVG_LEN_LOG  : integer := 2
    );
    port (
        i_clk         : in  std_logic;
        i_rst         : in  std_logic;
        -- input
        mavg_len_log  : in integer range 0 to MAX_MAVG_LEN_LOG;
        i_data_en     : in std_logic;
        i_data        : in std_logic_vector(9 downto 0);
        -- output
        o_data_valid  : out std_logic;
        o_data        : out std_logic_vector(9 downto 0));
end mavg;

architecture Behavioral of mavg is
    
    signal init_done : std_logic := '0';
    signal init_counter : integer range 0 to 1000 := 0;
    
    constant NB_Bit : integer := 14 + 9; -- 38 bit decimal / 10 bit (data)
    
    -- Signaux 
    signal delayed_signal_X_0 : signed (NB_Bit downto 0) := (others => '0');
    signal delayed_signal_X_1 : signed (NB_Bit downto 0) := (others => '0');
    signal delayed_signal_X_2 : signed (NB_Bit downto 0) := (others => '0');
    signal delayed_signal_Y_1 : signed (NB_Bit downto 0) := (others => '0');
    signal delayed_signal_Y_2 : signed (NB_Bit downto 0) := (others => '0');

    -- Signal de sortie



    signal Result : signed (NB_Bit*2+1 downto 0) := (others => '0'); -- pour 38 bit decimal (95 downto 0)
    
    constant coeff_0 : signed(NB_Bit downto 0):= X"003FBE"; -- Coefficients
    constant coeff_1 : signed(NB_Bit downto 0):= X"FF8087";
    constant coeff_2 : signed(NB_Bit downto 0):= X"003FBE";
    constant coeff_3 : signed(NB_Bit downto 0):= X"007F78";
    constant coeff_4 : signed(NB_Bit downto 0):= X"FFC082";




begin

process(i_clk)
    begin
         if init_done = '0' then
            if init_counter < 1000 then 
            	init_counter <= init_counter + 1;
            	delayed_signal_X_0 <= (others => '0');
            	delayed_signal_X_1 <= (others => '0');
            	delayed_signal_X_2 <= (others => '0');
            	delayed_signal_Y_1 <= (others => '0');
            	delayed_signal_Y_2 <= (others => '0'); 
            else 
            	init_done <= '1';
            end if;	     
        elsif rising_edge(i_clk) then
                delayed_signal_X_0 (NB_Bit downto NB_Bit-9) <= signed(i_data);  
                delayed_signal_X_0 (NB_Bit-10 downto 0) <= (others =>'0');
                delayed_signal_X_1 <= delayed_signal_X_0;
                delayed_signal_X_2 <= delayed_signal_X_1;
                       
                delayed_signal_Y_1 <= Result (NB_Bit*2-9 downto NB_Bit-9);
                --delayed_signal_Y_1 <= Result(NB_Bit*2-9 downto NB_Bit*2-18);
                delayed_signal_Y_2 <= delayed_signal_Y_1;
        end if;        
end process;

    Result <= (delayed_signal_X_0 * coeff_0) + 
             (delayed_signal_X_1 * coeff_1) + 
             (delayed_signal_X_2 * coeff_2) + 
             (delayed_signal_Y_1 * coeff_3) + 
             (delayed_signal_Y_2 * coeff_4);
 
    o_data <= std_logic_vector (delayed_signal_Y_1(NB_Bit downto NB_Bit-9));
    
end Behavioral;