#ifndef __STM32_TIMER_H #define __STM32_TIMER_H #define TIM_CR1_CKD_by1 0 #define TIM_CR1_CKD_by2 TIM_CR1_CKD_0 #define TIM_CR1_CKD_by4 TIM_CR1_CKD_1 #define TIM_CR1_ARPE_unbuffered 0 #define TIM_CR1_ARPE_buffered TIM_CR1_ARPE #define TIM_CR1_CMS_edge 0 #define TIM_CR1_CMS_center1 ( TIM_CR1_CKD_0) #define TIM_CR1_CMS_center2 (TIM_CR1_CKD_1 ) #define TIM_CR1_CMS_center3 (TIM_CR1_CKD_1|TIM_CR1_CKD_0) #define TIM_CR1_DIR_up 0 #define TIM_CR1_DIR_down TIM_CR1_DIR #define TIM_CR1_OPM_continuous 0 #define TIM_CR1_OPM_onepulse TIM_CR1_OPM #define TIM_CR1_URS_anyevent 0 #define TIM_CR1_URS_wrap TIM_CR1_URS #define TIM_CR1_UDIS_enabled 0 #define TIM_CR1_UDIS_disabled TIM_CR1_UDIS #define TIM_CR1_CEN_disabled 0 #define TIM_CR1_CEN_enabled TIM_CR1_CEN #define TIM_CR2_OIS4_low 0 #define TIM_CR2_OIS4_high TIM_CR2_O4S1 #define TIM_CR2_OIS3N_low 0 #define TIM_CR2_OIS3N_high TIM_CR2_O3S1N #define TIM_CR2_OIS3_low 0 #define TIM_CR2_OIS3_high TIM_CR2_O3S1 #define TIM_CR2_OIS2N_low 0 #define TIM_CR2_OIS2N_high TIM_CR2_O2S1N #define TIM_CR2_OIS2_low 0 #define TIM_CR2_OIS2_high TIM_CR2_O2S1 #define TIM_CR2_OIS1N_low 0 #define TIM_CR2_OIS1N_high TIM_CR2_OIS1N #define TIM_CR2_OIS1_low 0 #define TIM_CR2_OIS1_high TIM_CR2_OIS1 #define TIM_CR2_TI1S_channel1 0 #define TIM_CR2_TI1S_xor TIM_CR2_TI1S #define TIM_CR2_MMS_reset 0 #define TIM_CR2_MMS_enable ( TIM_CR2_MMS_0) #define TIM_CR2_MMS_update ( TIM_CR2_MMS_1 ) #define TIM_CR2_MMS_pulse ( TIM_CR2_MMS_1|TIM_CR2_MMS_0) #define TIM_CR2_MMS_compare1 (TIM_CR2_MMS_2 ) #define TIM_CR2_MMS_compare2 (TIM_CR2_MMS_2 |TIM_CR2_MMS_0) #define TIM_CR2_MMS_compare3 (TIM_CR2_MMS_2|TIM_CR2_MMS_1 ) #define TIM_CR2_MMS_compare4 (TIM_CR2_MMS_2|TIM_CR2_MMS_1|TIM_CR2_MMS_0) #define TIM_CR2_CCDS_channel 0 #define TIM_CR2_CCDS_update TIM_CR2_CCDS #define TIM_SMCR_ETP_noninv 0 #define TIM_SMCR_ETP_inverted TIM_SMCR_ETP #define TIM_SMCR_ECE_disabled 0 #define TIM_SMCR_ECE_enabled TIM_SMCR_ECE #define TIM_SMCR_ETPS_disabled 0 #define TIM_SMCR_ETPS_by2 ( TIM_SMCR_ETPS_0) #define TIM_SMCR_ETPS_by4 (TIM_SMCR_ETPS_1 ) #define TIM_SMCR_ETPS_by8 (TIM_SMCR_ETPS_1|TIM_SMCR_ETPS_0) #define TIM_SMCR_ETF_nofilter 0 #define TIM_SMCR_ETF_ckint_2 ( TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_ckint_4 ( TIM_SMCR_ETF_1 ) #define TIM_SMCR_ETF_ckint_6 ( TIM_SMCR_ETF_1|TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by2_6 ( TIM_SMCR_ETF_2 ) #define TIM_SMCR_ETF_by2_8 ( TIM_SMCR_ETF_2 |TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by4_6 ( TIM_SMCR_ETF_2|TIM_SMCR_ETF_1 ) #define TIM_SMCR_ETF_by4_8 ( TIM_SMCR_ETF_2|TIM_SMCR_ETF_1|TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by8_6 (TIM_SMCR_ETF_3 ) #define TIM_SMCR_ETF_by8_8 (TIM_SMCR_ETF_3 |TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by16_5 (TIM_SMCR_ETF_3 |TIM_SMCR_ETF_1 ) #define TIM_SMCR_ETF_by16_6 (TIM_SMCR_ETF_3 |TIM_SMCR_ETF_1|TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by16_8 (TIM_SMCR_ETF_3|TIM_SMCR_ETF_2 ) #define TIM_SMCR_ETF_by32_5 (TIM_SMCR_ETF_3|TIM_SMCR_ETF_2 |TIM_SMCR_ETF_0) #define TIM_SMCR_ETF_by32_6 (TIM_SMCR_ETF_3|TIM_SMCR_ETF_2|TIM_SMCR_ETF_1 ) #define TIM_SMCR_ETF_by32_8 (TIM_SMCR_ETF_3|TIM_SMCR_ETF_2|TIM_SMCR_ETF_1|TIM_SMCR_ETF_0) #define TIM_SMCR_MSM_nodelay 0 #define TIM_SMCR_MSM_delay TIM_SMCR_MSM #define TIM_SMCR_TS_itr0 0 #define TIM_SMCR_TS_itr1 ( TIM_SMCR_TS_0) #define TIM_SMCR_TS_itr2 ( TIM_SMCR_TS_1 ) #define TIM_SMCR_TS_itr3 ( TIM_SMCR_TS_1|TIM_SMCR_TS_0) #define TIM_SMCR_TS_edge (TIM_SMCR_TS_2 ) #define TIM_SMCR_TS_timer1 (TIM_SMCR_TS_2 |TIM_SMCR_TS_2) #define TIM_SMCR_TS_timer2 (TIM_SMCR_TS_2|TIM_SMCR_TS_1 ) #define TIM_SMCR_TS_external (TIM_SMCR_TS_2|TIM_SMCR_TS_1|TIM_SMCR_TS_0) #define TIM_SMCR_SMS_disabled 0 #define TIM_SMCR_SMS_encoder1 ( TIM_SMCR_SMS_0) #define TIM_SMCR_SMS_encoder2 ( TIM_SMCR_SMS_1 ) #define TIM_SMCR_SMS_encoder3 ( TIM_SMCR_SMS_1|TIM_SMCR_SMS_0) #define TIM_SMCR_SMS_reset (TIM_SMCR_SMS_2 ) #define TIM_SMCR_SMS_gated (TIM_SMCR_SMS_2 |TIM_SMCR_SMS_2) #define TIM_SMCR_SMS_trigger (TIM_SMCR_SMS_2|TIM_SMCR_SMS_1 ) #define TIM_SMCR_SMS_external (TIM_SMCR_SMS_2|TIM_SMCR_SMS_1|TIM_SMCR_SMS_0) #define TIM_CCMR1_OC2CE_none 0 #define TIM_CCMR1_OC2CE_cleared TIM_CCMR1_OC2CE #define TIM_CCMR1_OC2M_frozen 0 #define TIM_CCMR1_OC2M_set ( TIM_CCMR1_OC2M_0) #define TIM_CCMR1_OC2M_reset ( TIM_CCMR1_OC2M_1|TIM_CCMR1_OC2M_0) #define TIM_CCMR1_OC2M_toggle ( TIM_CCMR1_OC2M_1|TIM_CCMR1_OC2M_0) #define TIM_CCMR1_OC2M_force0 (TIM_CCMR1_OC2M_2 ) #define TIM_CCMR1_OC2M_force1 (TIM_CCMR1_OC2M_2 |TIM_CCMR1_OC2M_0) #define TIM_CCMR1_OC2M_pwm1 (TIM_CCMR1_OC2M_2|TIM_CCMR1_OC2M_1 ) #define TIM_CCMR1_OC2M_pwm2 (TIM_CCMR1_OC2M_2|TIM_CCMR1_OC2M_1|TIM_CCMR1_OC2M_0) #define TIM_CCMR1_OC2PE_anytime 0 #define TIM_CCMR1_OC2PE_preload TIM_CCMR1_OC2PE #define TIM_CCMR1_OC2FE_nofast #define TIM_CCMR1_OC2FE_fast TIM_CCMR1_OC2FE #define TIM_CCMR1_IC2F_ckint_2 ( TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_ckint_4 ( TIM_CCMR1_IC2F_1 ) #define TIM_CCMR1_IC2F_ckint_6 ( TIM_CCMR1_IC2F_1|TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by2_6 ( TIM_CCMR1_IC2F_2 ) #define TIM_CCMR1_IC2F_by2_8 ( TIM_CCMR1_IC2F_2 |TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by4_6 ( TIM_CCMR1_IC2F_2|TIM_CCMR1_IC2F_1 ) #define TIM_CCMR1_IC2F_by4_8 ( TIM_CCMR1_IC2F_2|TIM_CCMR1_IC2F_1|TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by8_6 (TIM_CCMR1_IC2F_3 ) #define TIM_CCMR1_IC2F_by8_8 (TIM_CCMR1_IC2F_3 |TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by16_5 (TIM_CCMR1_IC2F_3 |TIM_CCMR1_IC2F_1 ) #define TIM_CCMR1_IC2F_by16_6 (TIM_CCMR1_IC2F_3 |TIM_CCMR1_IC2F_1|TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by16_8 (TIM_CCMR1_IC2F_3|TIM_CCMR1_IC2F_2 ) #define TIM_CCMR1_IC2F_by32_5 (TIM_CCMR1_IC2F_3|TIM_CCMR1_IC2F_2 |TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2F_by32_6 (TIM_CCMR1_IC2F_3|TIM_CCMR1_IC2F_2|TIM_CCMR1_IC2F_1 ) #define TIM_CCMR1_IC2F_by32_8 (TIM_CCMR1_IC2F_3|TIM_CCMR1_IC2F_2|TIM_CCMR1_IC2F_1|TIM_CCMR1_IC2F_0) #define TIM_CCMR1_IC2PSC_none 0 #define TIM_CCMR1_IC2PSC_by2 ( TIM_CCMR2_IC2PSC_0) #define TIM_CCMR1_IC2PSC_by4 (TIM_CCMR1_IC2PSC_1 ) #define TIM_CCMR1_IC2PSC_by8 (TIM_CCMR1_IC2PSC_1|TIM_CCMR2_IC2PSC_0) #define TIM_CCMR1_CC2S_output 0 #define TIM_CCMR1_CC2S_inTI2 ( |TIM_CCMR1_CC2S_0) #define TIM_CCMR1_CC2S_inTI1 (TIM_CCMR1_CC2S_1 ) #define TIM_CCMR1_CC2S_inTRC (TIM_CCMR1_CC2S_1|TIM_CCMR1_CC2S_0) #define TIM_CCMR1_OC1CE_none 0 #define TIM_CCMR1_OC1CE_cleared TIM_CCMR1_OC1CE #define TIM_CCMR1_OC1M_frozen 0 #define TIM_CCMR1_OC1M_set ( TIM_CCMR1_OC1M_0) #define TIM_CCMR1_OC1M_reset ( TIM_CCMR1_OC1M_1|TIM_CCMR1_OC1M_0) #define TIM_CCMR1_OC1M_toggle ( TIM_CCMR1_OC1M_1|TIM_CCMR1_OC1M_0) #define TIM_CCMR1_OC1M_force0 (TIM_CCMR1_OC1M_2 ) #define TIM_CCMR1_OC1M_force1 (TIM_CCMR1_OC1M_2 |TIM_CCMR1_OC1M_0) #define TIM_CCMR1_OC1M_pwm1 (TIM_CCMR1_OC1M_2|TIM_CCMR1_OC1M_1 ) #define TIM_CCMR1_OC1M_pwm2 (TIM_CCMR1_OC1M_2|TIM_CCMR1_OC1M_1|TIM_CCMR1_OC1M_0) #define TIM_CCMR1_OC1PE_anytime 0 #define TIM_CCMR1_OC1PE_preload TIM_CCMR1_OC1PE #define TIM_CCMR1_OC1FE_nofast #define TIM_CCMR1_OC1FE_fast TIM_CCMR1_OC1FE #define TIM_CCMR1_IC1F_ckint_2 ( TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_ckint_4 ( TIM_CCMR1_IC1F_1 ) #define TIM_CCMR1_IC1F_ckint_6 ( TIM_CCMR1_IC1F_1|TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by2_6 ( TIM_CCMR1_IC1F_2 ) #define TIM_CCMR1_IC1F_by2_8 ( TIM_CCMR1_IC1F_2 |TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by4_6 ( TIM_CCMR1_IC1F_2|TIM_CCMR1_IC1F_1 ) #define TIM_CCMR1_IC1F_by4_8 ( TIM_CCMR1_IC1F_2|TIM_CCMR1_IC1F_1|TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by8_6 (TIM_CCMR1_IC1F_3 ) #define TIM_CCMR1_IC1F_by8_8 (TIM_CCMR1_IC1F_3 |TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by16_5 (TIM_CCMR1_IC1F_3 |TIM_CCMR1_IC1F_1 ) #define TIM_CCMR1_IC1F_by16_6 (TIM_CCMR1_IC1F_3 |TIM_CCMR1_IC1F_1|TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by16_8 (TIM_CCMR1_IC1F_3|TIM_CCMR1_IC1F_2 ) #define TIM_CCMR1_IC1F_by32_5 (TIM_CCMR1_IC1F_3|TIM_CCMR1_IC1F_2 |TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1F_by32_6 (TIM_CCMR1_IC1F_3|TIM_CCMR1_IC1F_2|TIM_CCMR1_IC1F_1 ) #define TIM_CCMR1_IC1F_by32_8 (TIM_CCMR1_IC1F_3|TIM_CCMR1_IC1F_2|TIM_CCMR1_IC1F_1|TIM_CCMR1_IC1F_0) #define TIM_CCMR1_IC1PSC_none 0 #define TIM_CCMR1_IC1PSC_by2 ( TIM_CCMR1_IC1PSC_0) #define TIM_CCMR1_IC1PSC_by4 (TIM_CCMR1_IC1PSC_1 ) #define TIM_CCMR1_IC1PSC_by8 (TIM_CCMR1_IC1PSC_1|TIM_CCMR1_IC1PSC_0) #define TIM_CCMR1_CC1S_output 0 #define TIM_CCMR1_CC1S_inTI1 ( |TIM_CCMR1_CC1S_0) #define TIM_CCMR1_CC1S_inTI2 (TIM_CCMR1_CC1S_1 ) #define TIM_CCMR1_CC1S_inTRC (TIM_CCMR1_CC1S_1|TIM_CCMR1_CC1S_0) #define TIM_CCMR2_OC4CE_none 0 #define TIM_CCMR2_OC4CE_cleared TIM_CCMR2_OC4CE #define TIM_CCMR2_OC4M_frozen 0 #define TIM_CCMR2_OC4M_set ( TIM_CCMR2_OC4M_0) #define TIM_CCMR2_OC4M_reset ( TIM_CCMR2_OC4M_1|TIM_CCMR2_OC4M_0) #define TIM_CCMR2_OC4M_toggle ( TIM_CCMR2_OC4M_1|TIM_CCMR2_OC4M_0) #define TIM_CCMR2_OC4M_force0 (TIM_CCMR2_OC4M_2 ) #define TIM_CCMR2_OC4M_force1 (TIM_CCMR2_OC4M_2 |TIM_CCMR2_OC4M_0) #define TIM_CCMR2_OC4M_pwm1 (TIM_CCMR2_OC4M_2|TIM_CCMR2_OC4M_1 ) #define TIM_CCMR2_OC4M_pwm2 (TIM_CCMR2_OC4M_2|TIM_CCMR2_OC4M_1|TIM_CCMR2_OC4M_0) #define TIM_CCMR2_OC4PE_anytime 0 #define TIM_CCMR2_OC4PE_preload TIM_CCMR2_OC4PE #define TIM_CCMR2_OC4FE_nofast #define TIM_CCMR2_OC4FE_fast TIM_CCMR2_OC4FE #define TIM_CCMR2_IC4F_ckint_2 ( TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_ckint_4 ( TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_ckint_6 ( TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by2_6 ( TIM_CCMR2_IC4F_2 ) #define TIM_CCMR2_IC4F_by2_8 ( TIM_CCMR2_IC4F_2 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by4_6 ( TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by4_8 ( TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by8_6 (TIM_CCMR2_IC4F_3 ) #define TIM_CCMR2_IC4F_by8_8 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by16_5 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by16_6 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by16_8 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2 ) #define TIM_CCMR2_IC4F_by32_5 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by32_6 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by32_8 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4PSC_none 0 #define TIM_CCMR2_IC4PSC_by2 ( TIM_CCMR2_IC4PSC_0) #define TIM_CCMR2_IC4PSC_by4 (TIM_CCMR2_IC4PSC_1 ) #define TIM_CCMR2_IC4PSC_by8 (TIM_CCMR2_IC4PSC_1|TIM_CCMR2_IC4PSC_0) #define TIM_CCMR2_CC4S_output 0 #define TIM_CCMR2_CC4S_inTI2 ( |TIM_CCMR2_CC4S_0) #define TIM_CCMR2_CC4S_inTI1 (TIM_CCMR2_CC4S_1 ) #define TIM_CCMR2_CC4S_inTRC (TIM_CCMR2_CC4S_1|TIM_CCMR2_CC4S_0) #define TIM_CCMR2_OC3CE_none 0 #define TIM_CCMR2_OC3CE_cleared TIM_CCMR2_OC3CE #define TIM_CCMR2_OC3M_frozen 0 #define TIM_CCMR2_OC3M_set ( TIM_CCMR2_OC3M_0) #define TIM_CCMR2_OC3M_reset ( TIM_CCMR2_OC3M_1|TIM_CCMR2_OC3M_0) #define TIM_CCMR2_OC3M_toggle ( TIM_CCMR2_OC3M_1|TIM_CCMR2_OC3M_0) #define TIM_CCMR2_OC3M_force0 (TIM_CCMR2_OC3M_2 ) #define TIM_CCMR2_OC3M_force1 (TIM_CCMR2_OC3M_2 |TIM_CCMR2_OC3M_0) #define TIM_CCMR2_OC3M_pwm1 (TIM_CCMR2_OC3M_2|TIM_CCMR2_OC3M_1 ) #define TIM_CCMR2_OC3M_pwm2 (TIM_CCMR2_OC3M_2|TIM_CCMR2_OC3M_1|TIM_CCMR2_OC3M_0) #define TIM_CCMR2_OC3PE_anytime 0 #define TIM_CCMR2_OC3PE_preload TIM_CCMR2_OC3PE #define TIM_CCMR2_OC3FE_nofast #define TIM_CCMR2_OC3FE_fast TIM_CCMR2_OC3FE #define TIM_CCMR2_IC4F_ckint_2 ( TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_ckint_4 ( TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_ckint_6 ( TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by2_6 ( TIM_CCMR2_IC4F_2 ) #define TIM_CCMR2_IC4F_by2_8 ( TIM_CCMR2_IC4F_2 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by4_6 ( TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by4_8 ( TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by8_6 (TIM_CCMR2_IC4F_3 ) #define TIM_CCMR2_IC4F_by8_8 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by16_5 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by16_6 (TIM_CCMR2_IC4F_3 |TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by16_8 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2 ) #define TIM_CCMR2_IC4F_by32_5 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2 |TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC4F_by32_6 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1 ) #define TIM_CCMR2_IC4F_by32_8 (TIM_CCMR2_IC4F_3|TIM_CCMR2_IC4F_2|TIM_CCMR2_IC4F_1|TIM_CCMR2_IC4F_0) #define TIM_CCMR2_IC1PSC_none 0 #define TIM_CCMR2_IC1PSC_by2 ( TIM_CCMR2_IC1PSC_0) #define TIM_CCMR2_IC1PSC_by4 (TIM_CCMR2_IC1PSC_1 ) #define TIM_CCMR2_IC1PSC_by8 (TIM_CCMR2_IC1PSC_1|TIM_CCMR2_IC1PSC_0) #define TIM_CCMR2_CC3S_output 0 #define TIM_CCMR2_CC3S_inTI1 ( |TIM_CCMR2_CC3S_0) #define TIM_CCMR2_CC3S_inTI2 (TIM_CCMR2_CC3S_1 ) #define TIM_CCMR2_CC3S_inTRC (TIM_CCMR2_CC3S_1|TIM_CCMR2_CC3S_0) #define TIM_CCER_CC4P_high 0 #define TIM_CCER_CC4P_low TIM_CCER_CC4P #define TIM_CCER_CC4E_disabled 0 #define TIM_CCER_CC4E_enabled TIM_CCER_CC4E #define TIM_CCER_CC3NP_high 0 #define TIM_CCER_CC3NP_low TIM_CCER_CC3NP #define TIM_CCER_CC3NE_disabled 0 #define TIM_CCER_CC3NE_enabled TIM_CCER_CC3NE #define TIM_CCER_CC3P_high 0 #define TIM_CCER_CC3P_low TIM_CCER_CC3P #define TIM_CCER_CC3E_disabled 0 #define TIM_CCER_CC3E_enabled TIM_CCER_CC3E #define TIM_CCER_CC2NP_high 0 #define TIM_CCER_CC2NP_low TIM_CCER_CC2NP #define TIM_CCER_CC2NE_disabled 0 #define TIM_CCER_CC2NE_enabled TIM_CCER_CC2NE #define TIM_CCER_CC2P_high 0 #define TIM_CCER_CC2P_low TIM_CCER_CC2P #define TIM_CCER_CC2E_disabled 0 #define TIM_CCER_CC2E_enabled TIM_CCER_CC2E #define TIM_CCER_CC1NP_high 0 #define TIM_CCER_CC1NP_low TIM_CCER_CC1NP #define TIM_CCER_CC1NE_disabled 0 #define TIM_CCER_CC1NE_enabled TIM_CCER_CC1NE #define TIM_CCER_CC1P_high 0 #define TIM_CCER_CC1P_low TIM_CCER_CC1P #define TIM_CCER_CC1E_disabled 0 #define TIM_CCER_CC1E_enabled TIM_CCER_CC1E #define TIM_BDTR_MOE_disabled 0 #define TIM_BDTR_MOE_enabled TIM_BDTR_MOE #define TIM_BDTR_AOE_software 0 #define TIM_BDTR_AOE_auto TIM_BDTR_AOE #define TIM_BDTR_BKP_low 0 #define TIM_BDTR_BKP_high TIM_BDTR_BKP #define TIM_BDTR_BKE_disabled 0 #define TIM_BDTR_BKE_enabled TIM_BDTR_BKE #define TIM_BDTR_OSSR_disabled 0 #define TIM_BDTR_OSSR_enabled TIM_BDTR_OSSR #define TIM_BDTR_OSSI_disabled 0 #define TIM_BDTR_OSSI_enabled TIM_BDTR_OSSI #define TIM_BDTR_LOCK_off 0 #define TIM_BDTR_LOCK_level1 ( TIM_BDTR_LOCK_0) #define TIM_BDTR_LOCK_level2 (TIM_BDTR_LOCK_1 ) #define TIM_BDTR_LOCK_level3 (TIM_BDTR_LOCK_1|TIM_BDTR_LOCK_0) #define TIM_BDTR_DT(n) (n) #define TIM_DCR_DBL_burst(n) (((n) & 0x1F) << 8) #define TIM_DCR_DBA_addr(addr) ((unsigned)(addr) & 0x1F) #endif //__STM32_TIMER_H