library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity testbench is
end entity testbench;



architecture test of testbench is

    signal simulation_run   : boolean   := true;

    constant tick_frequency : natural   := 10_000_000;
    constant tick_period    : time      := 1 sec / tick_frequency;

    signal tb_reference : signed (7 downto 0)   := "00000000";
    signal tb_feedback  : signed (7 downto 0)   := to_signed( 10, 8);
    signal tb_duty_out  : signed (7 downto 0);
    signal tb_tick      : std_logic             := '0';

begin

    tb_tick <= not tb_tick after tick_period / 2 when simulation_run;

    dut: entity work.pi
    port map
    (
        reference   => tb_reference,    -- : in signed (7 downto 0);
        feedback    => tb_feedback,     -- : in signed (7 downto 0);
        duty_out    => tb_duty_out,     -- : out signed (7 downto 0);
        tick        => tb_tick          -- : in std_logic
    );

    process
    begin
        wait for tick_period * 20;

        for value in -100 to 100 loop
            tb_reference    <= to_signed(  value, tb_reference'length);
            tb_feedback     <= to_signed( -value, tb_feedback'length);
            wait for tick_period * 10;
        end loop;

        simulation_run <= false;
        report "Simulation end.";
        wait; -- forever
    end process;


end architecture test;