library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity zahl_einsen_lothar is
	generic
	(
		G_DATA_WIDTH           : natural
	);
	port
	(
		i_data                 : in  std_logic_vector(7 downto 0);
		o_valid_bytes          : out std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0)
	);
end zahl_einsen_lothar;

architecture rtl of zahl_einsen_lothar is

begin

	process (i_data)
		variable x : std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0);
	begin
	
		x := (others => '0'); 
		x(to_integer(unsigned(i_data))) := '1'; 
		o_valid_bytes <= std_logic_vector(unsigned(x) - 1);
	
	end process;

end;