library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity zahl_einsen_alex is
	generic
	(
		G_DATA_WIDTH           : natural
	);
	port
	(
		i_data                 : in  std_logic_vector(7 downto 0);
		o_valid_bytes          : out std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0)
	);
end zahl_einsen_alex;

architecture rtl of zahl_einsen_alex is

begin

	process (i_data)
	begin

		for i in 0 to G_DATA_WIDTH/8 - 1 loop
			if i < unsigned(i_data) then
				o_valid_bytes(i) <= '1';
			else
				o_valid_bytes(i) <= '0';
			end if;
		end loop;

	end process;

end;