library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_zahl_einsen is
	generic
	(
		G_DATA_WIDTH           : natural := 64
	);
	port
	(
		i_data                 : in  std_logic_vector(7 downto 0);
		o_valid_bytes_alex     : out std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0);
		o_valid_bytes_lothar   : out std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0);
		o_valid_bytes_gustl    : out std_logic_vector(G_DATA_WIDTH/8 - 1 downto 0)
	);
end top_zahl_einsen;

architecture rtl of top_zahl_einsen is

begin

	inst_zahl_einsen_alex : entity work.zahl_einsen_alex
		generic map
		(
			G_DATA_WIDTH           => G_DATA_WIDTH
		)
		port map
		(
			i_data                 => i_data,
			o_valid_bytes          => o_valid_bytes_alex
		);
		
	inst_zahl_einsen_lothar : entity work.zahl_einsen_lothar
		generic map
		(
			G_DATA_WIDTH           => G_DATA_WIDTH
		)
		port map
		(
			i_data                 => i_data,
			o_valid_bytes          => o_valid_bytes_lothar
		);
		
	inst_zahl_einsen_gustl : entity work.zahl_einsen_gustl
		generic map
		(
			G_DATA_WIDTH           => G_DATA_WIDTH
		)
		port map
		(
			i_data                 => i_data,
			o_valid_bytes          => o_valid_bytes_gustl
		);

end;