library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_zahl_einsen is
end tb_zahl_einsen;

architecture tb of tb_zahl_einsen is

	constant C_DATA_WIDTH     : natural := 64;
	
	signal data               : std_logic_vector(7 downto 0) := (others => '0');
	signal valid_bytes_alex   : std_logic_vector(C_DATA_WIDTH/8 - 1 downto 0) := (others => '0');
	signal valid_bytes_lothar : std_logic_vector(C_DATA_WIDTH/8 - 1 downto 0) := (others => '0');
	signal valid_bytes_gustl  : std_logic_vector(C_DATA_WIDTH/8 - 1 downto 0) := (others => '0');

begin

	process
	begin
	wait for 10 ns;
		data <= x"04";
	wait for 10 ns;
		data <= x"07";
	wait;
	end process;

	inst_top_zahl_einsen : entity work.top_zahl_einsen
		generic map
		(
			G_DATA_WIDTH           => C_DATA_WIDTH
		)
		port map
		(
			i_data                 => data,
			o_valid_bytes_alex     => valid_bytes_alex,
			o_valid_bytes_lothar   => valid_bytes_lothar,
			o_valid_bytes_gustl    => valid_bytes_gustl
		);

end;