library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sub_add_tb is end entity; architecture test of sub_add_tb is signal clk : std_logic := '0'; signal sub : std_logic; signal in_1 : signed(7 downto 0); signal in_2 : signed(7 downto 0); signal res : signed(7 downto 0); begin clk <= not clk after 5 ns; -- Generate 100 MHz clock, changes polarity every 5 nanoseconds sig_proc : process begin -- Set initial values sub <= '0'; in_1 <= (others => '0'); in_2 <= (others => '0'); wait for 50 ns; in_1 <= to_signed(5, in_1'length); -- Change operand 1 wait for 20 ns; in_2 <= to_signed(7, in_2'length); -- Change operad 2 wait for 20 ns; sub <= '1'; -- Change mode to subtract -- And so on wait; end process; -- The adder/subtractor connected to the signals defined above sub_add_dut : entity work.sub_add port map( clk => clk, sub => sub, in_1 => in_1, in_2 => in_2, res => res ); end architecture;