library IEEE;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sub_add is
	port(
		clk		: in  std_logic;
		sub		: in  std_logic;
		in_1	: in  signed(7 downto 0);
		in_2	: in  signed(7 downto 0);
		res		: out signed(7 downto 0)
	);
end entity;

architecture rtl of sub_add is
begin
	
	process
	begin
		wait until rising_edge(clk);	-- Can be synthesised in this case
		if sub = '0' then
			res <= in_1 + in_2;
		else
			res <= in_1 - in_2;
		end if;
	end process;
	
	-- Same functionality as above
	process(clk)	-- Only start on changes of clk
	begin
		if rising_edge(clk) then
			if sub = '0' then
				res <= in_1 + in_2;
			else
				res <= in_1 - in_2;
			end if;
		end if;
	end process;
		
end architecture;