library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity t_DDR is

end t_DDR;

architecture RTL of t_DDR is
	component DDR is
		port (
				ALARM_TIME 		: in std_logic_vector (3 downto 0);
				CURRENT_TIME 	: in std_logic_vector (3 downto 0);
				SHOW_A			: in std_logic;
				-----
				DISPLAY			: out std_logic_vector (6 downto 0);
				SOUND_ALARM		: out std_logic
			);
	end component;

		signal ALARM_TIME 		: std_logic_vector (3 downto 0);
		signal CURRENT_TIME 	: std_logic_vector (3 downto 0);
		signal SHOW_A			: std_logic;
		signal DISPLAY			: std_logic_vector (6 downto 0);
		signal SOUND_ALARM		: std_logic;
		signal DISP_ALARM		: std_logic_vector (6 downto 0);
		signal DISP_CURRENT		: std_logic_vector (6 downto 0);
		
		begin
	
		uut : DDR port map
			(
				ALARM_TIME		=> ALARM_TIME,
				CURRENT_TIME 	=> CURRENT_TIME,
				SHOW_A		 	=> SHOW_A,
				DISPLAY		 	=> DISPLAY,
				SOUND_ALARM 	=> SOUND_ALARM
			);
			
		process
			begin
		
				ALARM_TIME 		<= "0110";
				CURRENT_TIME 	<= "1001";
				SHOW_A 			<= '1';
				wait for 20ns;
				
				ALARM_TIME 		<= "0111";
				CURRENT_TIME 	<= "1000";
				SHOW_A 			<= '0';
				wait for 20ns;
				
				ALARM_TIME 		<= "0011";
				CURRENT_TIME 	<= "0000";
				SHOW_A 			<= '1';
				wait for 20ns;
				
				ALARM_TIME 		<= "0111";
				CURRENT_TIME 	<= "0110";
				SHOW_A 			<= '0';
				wait for 20ns;
				
				ALARM_TIME 		<= "0001";
				CURRENT_TIME 	<= "0001";
				SHOW_A 			<= '1';
				wait for 20ns;
		
			wait;
		
		end process;
	
	end RTL;