library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t_DDRV is end t_DDRV; architecture RTL of t_DDRV is component DDRV is port ( ALARM_TIME : in std_logic_vector (3 downto 0); CURRENT_TIME : in std_logic_vector (3 downto 0); SHOW_A : in std_logic; ----- DISPLAY : out std_logic_vector (6 downto 0); SOUND_ALARM : out std_logic ); end component; signal ALARM_TIME : std_logic_vector (3 downto 0); signal CURRENT_TIME : std_logic_vector (3 downto 0); signal SHOW_A : std_logic; signal DISPLAY : std_logic_vector (6 downto 0); signal SOUND_ALARM : std_logic; begin uut : DDRV port map ( ALARM_TIME => ALARM_TIME, CURRENT_TIME => CURRENT_TIME, SHOW_A => SHOW_A, DISPLAY => DISPLAY, SOUND_ALARM => SOUND_ALARM ); process begin ALARM_TIME <= "0110"; CURRENT_TIME <= "1001"; SHOW_A <= '1'; wait for 20ns; ALARM_TIME <= "0111"; CURRENT_TIME <= "1000"; SHOW_A <= '0'; wait for 20ns; ALARM_TIME <= "1111"; CURRENT_TIME <= "0000"; SHOW_A <= '1'; wait for 20ns; ALARM_TIME <= "1110"; CURRENT_TIME <= "0110"; SHOW_A <= '0'; wait for 20ns; ALARM_TIME <= "1111"; CURRENT_TIME <= "1111"; SHOW_A <= '1'; wait for 20ns; wait; end process; end RTL;