library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity counter_tb is
end entity counter_tb;


architecture testbench of counter_tb is

    signal   simulation_run     : boolean := true;

    constant tb_clk_frequency   : natural := 10_000_000; -- MHz
    constant tb_clk_period      : time := 1 sec / tb_clk_frequency;

    signal tb_clk     : std_logic := '0';
    signal tb_sig1    : std_logic;
    signal tb_sig2    : std_logic;
    signal tb_sig3    : std_logic;

begin

    tb_clk <= not tb_clk after tb_clk_period / 2 when simulation_run;

    dut: entity work.counter
    port map
    (
        clk     => tb_clk,    -- : in  std_logic;
        sig1    => tb_sig1,   -- : out std_logic;
        sig2    => tb_sig2,   -- : out std_logic;
        sig3    => tb_sig3    -- : out std_logic
    );

    process
    begin
        wait for 1 ms;
        simulation_run <= false;
        report "Simulation stopped.";
        wait;
    end process;

end architecture testbench;