library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity counter is
port
(
    clk     : in  std_logic;
    sig1    : out std_logic;
    sig2    : out std_logic;
    sig3    : out std_logic
);
end entity counter;

architecture rtl of counter is

    constant sig1_on    : natural := 100;
    constant sig1_off   : natural := 200;
    constant sig2_on    : natural := 100;
    constant sig2_off   : natural := 101;
    constant sig3_on    : natural := 888;
    constant sig3_off   : natural := 999;

    signal counter      : unsigned( 11 downto 0) := ( others => '0');

begin

    process
    begin
        wait until rising_edge( clk);

        if counter = sig1_on then
            sig1    <= '1';
        end if;
        if counter = sig1_off then
            sig1    <= '0';
        end if;


        if counter = sig2_on then
            sig2    <= '1';
        end if;
        if counter = sig2_off then
            sig2    <= '0';
        end if;

        if counter = sig3_on then
            sig3    <= '1';
        end if;
        if counter = sig3_off then
            sig3    <= '0';
        end if;

        counter <= counter + 1;

    end process;

end architecture rtl;