Library IEEE;
use IEEE.std_logic_1164.all;
entity reg1 is
port (Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q1,Q2,Q3,Q4 : out STD_LOGIC); 
end reg1;
architecture reg1_arch of reg1 is
signal sq1,sq2,sq3,sq4: STD_LOGIC; begin 
process (Clk, reset) is
begin 
   if ( reset = '0' ) then
                 sq1 <='1';
        sq2<='0';
        sq3<='0';
                  sq4<='0';
  elsif (rising_edge(Clk)) then
                                     sq1<=sq1;
                                     sq2<=sq2;
                                     sq3<=sq3;
                                     sq4<=sq4;
   end if;
end process;  
Q1<=sq1;
Q2<=sq2;
Q3<=sq3;
Q4<=sq4;
end reg1_arch;