-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS type intarray_t is array (0 to 3) of integer; constant data : intarray_t := (20,40,10,30); signal rank : intarray_t := ( 0, 0, 0, 0); BEGIN process begin for idx in 0 to 3 loop for i in 0 to 3 loop if data(idx)>data(i) then rank(idx) <= rank(idx)+1; wait for 1 ns; -- update signals end if; end loop; end loop; wait; -- will wait forever end process; END;